3.11.1 Cold Load Pickup Logic Theory
The cold load pickup (CLP) logic which is included within this relay serves to either inhibit the selected protective elements for an appointed duration, or to raise the settings of the selected protective elements. Therefore, it allows the protection settings to be set closer to the load profile by automatically increasing them following circuit energization. The CLP logic thus provides stability, whilst maintaining protection during starting.
The CLP function acts upon the overcurrent protection and the No.1 group of zero sequence overcurrent protection. The output signal of the CLP logic also can be used as a blocking signal for a selected protective element through the PCS-Explorer configuration tool software.
The logic diagram of the cold load pickup function is shown in Figure 3.11-1.
The cold load pickup logic operates when the circuit breaker remains open for a time greater than [CLP.t_Cold] and is subsequently closed. The CLP operation is applied after [CLP.t_Cold] and remains for a time delay [CLP.t_Rst] after the circuit breaker is closed. The status of the circuit breaker is provided either by means of the load current ([CLP.LogicMode] = 1) or by means of the
CB auxiliary contact ([CLP.LogicMode] = 2). The signal [CLP.OnLoad] can be gotten from the signal “Prot.OnLoad” through the PCS-Explorer.
If the CLP output “CLP.St” is “1”, the CLP settings are enabled for the overcurrent protection and the No.1 group of zero sequence overcurrent protection respectively. After the delay [CLP.t_Rst]
has elapsed, the normal protection settings are applied. And if a fast resetting signal is received, the normal protection settings are applied after the delay [CLP.t_ShortRst].
[CLP.St]
Figure 3.11-1 Logic diagram of the cold load pickup function
Where:
[CLP.OnLoad] is the signal denotes anyone of the phase currents is greater than 0.04In;
[CLP.LogicMode] is used for selecting the cold load condition mode;
[BI_52b] is the binary input for inputting the normally closed contact of the circuit breaker;
[CLP.ShortRst] is the binary signal of the short resetting function;
[CLP.St_50/51] is the binary signal which denotes anyone of the selected protective elements picked up;
[CLP.Init] is the binary signal for initiating the cold load pickup logic function (for example, a binary input signal from other relevant relay);
[CLP.En] is the logic setting of the cold load pickup logic function;
[CLP.Blk] is the binary signal for blocking the cold load pickup logic function;
“tCold” is the setting [CLP.t_Cold], the time setting for ensuring the cold load condition is met;
“tRst” is the setting [CLP.t_Rst], the time setting for resetting the cold load pickup logic function;
“tShortRst” is the setting [CLP.t_ShortRst], the time setting for fast resetting the cold load pickup logic function.
3.11.2 Cold Load Pickup Logic Settings
All the settings of the cold load pickup logic are listed in the following table. For the information
about the common explanation of the settings, see Section 7.3.
No. Menu text Explanation Range Step
1 CLP.Opt_LogicMode The setting for selecting the cold load condition 1~2 1
2 CLP.t_Cold The time setting for ensuring the cold load
condition is met 0~4000s 0.001s
3 CLP.t_Rst The time setting for resetting the cold load pickup
logic 0~4000s 0.001s
4 CLP.t_ShortRst The time setting for fast resetting the cold load
pickup logic 0~600s 0.001s
5 CLP.En The logic setting of the cold load pickup logic
function 0~1 1
6 50/51P1.CLP.IMult The multiple setting of the stage 1 overcurrent
protection when CLP is active 1.00~10.00 0.001
7 50/51P1.CLP.t_Op The time setting of the stage 1 overcurrent
protection when CLP is active 0~100s 0.001s
8 50/51P2.CLP.IMult The multiple setting of the stage 2 overcurrent
protection when CLP is active 1.00~10.00 0.001
9 50/51P2.CLP.t_Op The time setting of the stage 2 overcurrent
protection when CLP is active 0~100s 0.001s
10 50/51P3.CLP.IMult The multiple setting of the stage 3 overcurrent
protection when CLP is active 1.00~10.00 0.001
11 50/51P3.CLP.t_Op The time setting of the stage 3 overcurrent
protection when CLP is active 0~100s 0.001s
12 50/51P4.CLP.IMult The multiple setting of the stage 4 overcurrent
protection when CLP is active 1.00~10.00 0.001
13 50/51P4.CLP.t_Op The time setting of the stage 4 overcurrent
protection when CLP is active 0~100s 0.001s
14 50/51P4.CLP.TMS The time multiplier setting of the IDMT overcurrent
protection when CLP is active 0.05~100.0 0.001
15 50/51G1.CLP.IMult The multiple setting of the stage 1 zero sequence
overcurrent protection when CLP is active 1.00~10.00 0.001
16 50/51G1.CLP.t_Op The time setting of the stage 1 zero sequence
overcurrent protection when CLP is active 0~100s 0.001s
17 50/51G2.CLP.IMult The multiple setting of the stage 2 zero sequence
overcurrent protection when CLP is active 1.00~10.00 0.001
18 50/51G2.CLP.t_Op The time setting of the stage 2 zero sequence
overcurrent protection when CLP is active 0~100s 0.001s
19 50/51G3.CLP.IMult The multiple setting of the stage 3 zero sequence
overcurrent protection when CLP is active 1.00~10.00 0.001
20 50/51G3.CLP.t_Op The time setting of the stage 3 zero sequence
overcurrent protection when CLP is active 0~100s 0.001s
21 50/51G4.CLP.IMult The multiple setting of the stage 4 zero sequence
overcurrent protection when CLP is active 1.00~10.00 0.001
22 50/51G4.CLP.t_Op The time setting of the stage 4 zero sequence
overcurrent protection when CLP is active 0~100s 0.001s
23 50/51G1.CLP.TMS The time multiplier setting of the zero sequence
IDMT overcurrent protection when CLP is active 0.05~100.0 0.001
3.12 Undervoltage Protection
3.12.1 Undervoltage Protection Theory
This relay provides a two-stage undervoltage protection with definite time delay characteristics.
The two stages have same protection logics. Each stage can be used for tripping or alarming through the PCS-Explorer and the default is for tripping.
This protection can support all kinds of VT connection: three phase voltage (Ua, Ub, Uc), three phase-to-phase voltages (Uab, Ubc, Uca), two phase-to-phase voltages (Uab, Ubc), anyone of three phase voltages or anyone of three phase-to-phase voltages.
Two methods are used to check the undervoltage condition by the setting [27P.Opt_1P/3P]. If setting [27P.Opt_1P/3P] is set as “0”, and all of the three voltage values are less than the voltage setting, the undervoltage protection will operates after the appointed time delay; and if the setting [27P.Opt_1P/3P] is set as “1”, and anyone of the three voltage values is less than the voltage setting, the undervoltage protection will operates after the appointed time delay.
The setting [27P.Opt_Up/Upp] is used to decide the voltage input mode. If it is set as “1”, the input voltage is phase-to-phase voltage; and if it is set as “0”, the input voltage is phase voltage. So the voltage setting must be set in accordance with the setting [27P.Opt_Up/Upp]; i.e. if the setting [27P.Opt_Up/Upp] is set as “1”, the voltage setting is set according to phase-to-phase voltage; and if the setting [27P.Opt_Up/Upp] is set as “0”, the voltage setting is set according to phase voltage.
The circuit breaker state (based on the binary input [BI_52b]) is taken into account in the undervoltage protection logic; when the circuit breaker is opened ([BI_52b] = 1), the undervoltage protection is not in service.
If the system voltage is lost, the undervoltage protection is blocked. The criterion of the system voltage lost detects that all the three phase voltages are less than 15V, and the load current can be taken into account according to the application demands through [27P1.OnLoad] which denotes whether there has load current (anyone of the three phase currents is greater than 0.04In). The signal [27P1.OnLoad] can be gotten from the signal “Prot.OnLoad” through the PCS-Explorer.
Figure 3.12-1 Logic diagram of the system lost voltage for the UV1 protection The following figure shows the logic diagram of the stage 1 undervoltage protection.
Figure 3.12-2 Logic diagram of the stage 1 undervoltage protection
Where:
[27P1.U_Set] is the voltage setting of the stage 1 undervoltage protection;
“tUV1” is the setting [27P1.t_Op], the time setting of the stage 1 undervoltage protection;
[27P.Opt_1P/3P] is the logic setting for selecting the undervoltage calculation method;
[27P.Opt_Up/Upp] is the logic setting for deciding the voltage input mode;
[27P1.En] is the logic setting of the stage 1 undervoltage protection;
[27P1.En1] is the binary signal for enabling the stage 1 undervoltage protection;
[27P1.Blk] is the binary signal for blocking the stage 1 undervoltage protection;
[BI_52b] is the binary input from the auxiliary normally closed contact of the circuit breaker;
“27P1.LostVolt” denotes whether the system voltage is lost.
3.12.2 Undervoltage Protection Settings
All the settings of the undervoltage protections are listed in the following table. For the information about the common explanation of the settings, see Section 7.3.
No. Menu text Explanation Range Step
1 27P.Opt_1P/3P The setting for selecting the undervoltage
protection calculation method 0~1 1
2 27P.Opt_Up/Upp The setting for selecting the voltage input mode
for the undervoltage protection 0~1 1
3 27P1.U_Set The voltage setting of the stage 1 undervoltage
protection 2~120V 0.001V
4 27P1.t_Op The time setting of the stage 1 undervoltage
protection 0~100s 0.001s
5 27P1.K_DropOut The dropout coefficient setting of the stage 1
undervoltage protection 1.03~3.0 0.001
6 27P1.En The logic setting of the stage 1 undervoltage
protection 0~1 1
7 27P1.OutMap The output matrix setting of the stage 1 undervoltage protection
0x00000000 ~ 0x7FFFFFFF 1
8 27P2.U_Set The voltage setting of the stage 2 undervoltage
protection 2~120V 0.001V
9 27P2.t_Op The time setting of the stage 2 undervoltage
protection 0~100s 0.001s
10 27P2.K_DropOut The dropout coefficient setting of the stage 2
undervoltage protection 1.03~3.0 0.001
11 27P2.En The logic setting of the stage 2 undervoltage
protection 0~1 1
12 27P2.OutMap The output matrix setting of the stage 2 undervoltage protection
0x00000000 ~ 0x7FFFFFFF 1
If the voltage is greater than [27Px.U_Set]×[27Px.K_DropOut] (x: 1~2), the corresponding undervoltage protection will drop out. The dropout coefficient [27Px.K_DropOut] (x: 1~2) for setting the dropout value of the corresponding undervoltage protection, and its typical value is “1.03”.
3.13 Overvoltage Protection
3.13.1 Overvoltage Protection Theory
This relay provides a two-stage overvoltage protection with definite time delay characteristics. The two stages have same protection logics. Each stage can be used for tripping or alarming through the PCS-Explorer and the default is for tripping.
This protection can support all kinds of VT connection: three phase voltage (Ua, Ub, Uc), three phase-to-phase voltages (Uab, Ubc, Uca), two phase-to-phase voltages (Uab, Ubc), anyone of three phase voltages or anyone of three phase-to-phase voltages.
Two methods are used to check the overvoltage condition by the setting [59P.Opt_1P/3P]. If setting [59P.Opt_1P/3P] is set as “0”, and all of the three voltage values are greater than the voltage setting, the overvoltage protection will operates after the appointed time delay; and if the setting [59P.Opt_1P/3P] is set as “1”, and anyone of the three voltage values is greater than the voltage setting, the overvoltage protection will operates after the appointed time delay.
The setting [59P.Opt_Up/Upp] is used to decide the voltage input mode. If it is set as “1”, the input voltage is phase-to-phase voltage; and if it is set as “0”, the input voltage is phase voltage. So the voltage setting must be set in accordance with the setting [59P.Opt_Up/Upp]; i.e. if the setting [59P.Opt_Up/Upp] is set as “1”, the voltage setting is set according to phase-to-phase voltage; and if the setting [59P.Opt_Up/Upp] is set as “0”, the voltage setting is set according to phase voltage.
The following figure shows the logic diagram of the stage 1 overvoltage protection.
Figure 3.13-1 Logic diagram of the stage 1 overvoltage protection
Where:
[59P1.U_Set] is the voltage setting of the stage 1 overvoltage protection;
“tOV1” is the setting [59P1.t_Op], the time setting of the stage 1 overvoltage protection;
[59P.Opt_1P/3P] is the logic setting for selecting the overvoltage calculation method;
[59P.Opt_Up/Upp] is the logic setting for deciding the voltage input mode;
[59P1.En] is the logic setting of the stage 1 overvoltage protection;
[59P1.En1] is the binary signal for enabling the stage 1 overvoltage protection;
[59P1.Blk] is the binary signal for blocking the stage 1 overvoltage protection.
3.13.2 Overvoltage Protection Settings
All the settings of the overvoltage and undervoltage protections are listed in the following table. For the information about the common explanation of the settings, see Section 7.3.
No. Menu text Explanation Range Step
1 59P.Opt_1P/3P The setting for selecting the overvoltage
protection calculation method 0~1 1
2 59P.Opt_Up/Upp The setting for selecting the voltage input mode
for the overvoltage protection 0~1 1
3 59P1.U_Set The voltage setting of the stage 1 overvoltage
protection 57.7~200V 0.001V
4 59P1.t_Op The time setting of the stage 1 overvoltage
protection 0~100s 0.001s
5 59P1.K_DropOut The dropout coefficient setting of the stage 1
overvoltage protection 0.93~0.97 0.001
6 59P1.En The logic setting of the stage 1 overvoltage
protection 0~1 1
7 59P1.OutMap The output matrix setting of the stage 1 overvoltage protection
0x00000000 ~ 0x7FFFFFFF 1
8 59P2.U_Set The voltage setting of the stage 2 overvoltage
protection 57.7~200V 0.001V
9 59P2.t_Op The time setting of the stage 2 overvoltage
protection 0~100s 0.001s
10 59P2.K_DropOut The dropout coefficient setting of the stage 2
overvoltage protection 0.93~0.97 0.001
11 59P2.En The logic setting of the stage 2 overvoltage
protection 0~1 1
12 59P2.OutMap The output matrix setting of the stage 2 overvoltage protection
0x00000000 ~ 0x7FFFFFFF 1
If the voltage is less than [59Px.U_Set]×[59Px.K_DropOut] (x: 1~2), the corresponding overvoltage protection will drop out. The dropout coefficient [59Px.K_DropOut] (x: 1~2) for setting the dropout value of the corresponding overvoltage protection, and its typical value is “0.97”.
3.14 Zero Sequence Overvoltage Protection
3.14.1 Zero Sequence Overvoltage Protection Theory
On a healthy three-phase power system, the addition of each of the three-phase to earth voltages is nominally zero. However, when an earth fault occurs on the primary system, the balance is upset and a residual voltage is produced. Hence, a zero sequence overvoltage protection can be used to offer earth fault protection on such a system.
The residual voltage could be measured at the secondary terminals of a voltage transformer having a “broken delta” secondary connection, or it can be calculated from the three phase voltages; which is decided by the setting [Opt_3U0].
This relay provides a two-stage zero sequence overvoltage protection with definite time delay characteristics. The two stages have same protection logics.
The following figure shows the logic diagram of the stage 1 zero sequence overvoltage protection.
Figure 3.14-1 Logic diagram of the stage 1 ROV protection Where:
[59G1.3U0_Set] is the voltage setting of the stage 1 zero sequence overvoltage protection;
“tROV1” is the setting [59G1.t_Op], the time setting of the stage 1 zero sequence overvoltage protection;
[59G1.En] is logic setting of the stage 1 zero sequence overvoltage protection.
[59G1.En1] is the binary signal for enabling the stage 1 zero sequence overvoltage protection;
[59G1.Blk] is the binary signal for blocking the stage 1 zero sequence overvoltage protection.
3.14.2 Zero Sequence Overvoltage Protection Settings
All the settings of the zero sequence overvoltage protection are listed in the following table. For the information about the common explanation of the settings, see Section 7.3.
No. Menu text Explanation Range Step
1 59G1.3U0_Set The voltage setting of the stage 1 zero sequence
overvoltage protection 2~160V 0.001V
2 59G1.t_Op The time setting of the stage 1 zero sequence
overvoltage protection 0~100s 0.001s
3 59G1.En The logic setting of the stage 1 zero sequence
overvoltage protection 0~1 1
4 59G1.OutMap The output matrix setting of the stage 1 zero sequence overvoltage protection
0x00000000 ~ 0x7FFFFFFF 1
5 59G2.3U0_Set The voltage setting of the stage 2 zero sequence
overvoltage protection 2~160V 0.001V
6 59G2.t_Op The time setting of the stage 2 zero sequence
overvoltage protection 0~100s 0.001s
7 59G2.En The logic setting of the stage 2 zero sequence
overvoltage protection 0~1 1
8 59G2.OutMap The output matrix setting of the stage 2 zero sequence overvoltage protection
0x00000000 ~ 0x7FFFFFFF 1
3.15 Negative Sequence Overvoltage Protection
3.15.1 Negative Sequence Overvoltage Protection Theory
On a healthy three-phase power system, the negative sequence voltage is nominally zero.
However, when an unbalance situation occurs on the primary system, the negative sequence voltage is produced.
This relay provides a one-stage negative sequence overvoltage protection with definite time delay characteristic. The negative sequence voltage is self-calculated.
The following figure shows the logic diagram of the negative sequence overvoltage protection.
Figure 3.15-1 Logic diagram of the NOV protection
Where:
[59Q.U2_Set] is the voltage setting of the negative sequence overvoltage protection;
“tNOV” is the setting [59Q.t_Op], the time setting of the negative sequence overvoltage protection;
[59Q.En] is logic setting of the negative sequence overvoltage protection.
[59Q.En1] is the binary signal for enabling the negative sequence overvoltage protection;
[59Q.Blk] is the binary signal for blocking the negative sequence overvoltage protection.
3.15.2 Negative Sequence Overvoltage Protection Settings
All the settings of the negative sequence overvoltage protection are listed in the following table.
For the information about the common explanation of the settings, see Section 7.3.
No. Menu text Explanation Range Step
1 59Q.U2_Set The voltage setting of the negative sequence
overvoltage protection 2~120V 0.001V
2 59Q.t_Op The time setting of the negative sequence
overvoltage protection 0~100s 0.001s
3 59Q.En The logic setting of the negative sequence
overvoltage protection 0~1 1
4 59Q.OutMap The output matrix setting of the negative sequence overvoltage protection
0x00000000 ~ 0x7FFFFFFF 1
3.16 Frequency Protection
The frequency protection detects abnormally high and low frequencies in the power system or in electrical machines. If the frequency is out of the allowable range, the appropriate actions are initiated, such as load shedding or separating a generator from the system.
A decrease in system frequency occurs when the system experiences an increase in the real power demand, or when a malfunction occurs with a generator governor or automatic generation control (AGC) system. The frequency protection function is also used for generators, which (for a certain time) operate to an island network. This is due to the fact that the reverse power protection cannot operate in case of a drive power failure. The generator can be disconnected from the power system using the frequency decrease protection.
An increase in system frequency occurs, e.g. when large blocks of load (island network) are
removed from the system, or again when a malfunction occurs with a generator governor. This entails risk of self-excitation for generators feeding long lines under no-load conditions.
The calculation of the frequency is based on the voltage sampled values. Four cycles of the voltage sampled values are fixedly adopted for the frequency calculation.
3.16.1 Under-frequency Protection
The feeder relay includes under-frequency protection to facilitate load shedding and subsequent restoration. It provides a four-stage under-frequency protection with independent definite time delay characteristics in this relay, and the four stages have same protection logics.
This protection can be enabled after 100ms only when the frequency is greater than the frequency setting [81Ux.f_Set] (x: 1~4) and three phase-to-phase voltages are greater than the setting [81.Upp_VCE]. Meanwhile, this protection will be blocked when the system frequency is less than 35.00Hz or greater than 70.00Hz and this situation keeps for longer than 200ms.
The logic diagram of the stage 1 under-frequency protection is shown as below.
Figure 3.16-1 Logic diagram of the stage 1 under-frequency protection
Where:
[81U1.f_Set] is the frequency setting of the stage 1 under-frequency protection;
“tUF1” is the setting [81U1.t_Op], the time setting of the stage 1 under-frequency protection;
[81.Upp_VCE] is the under voltage blocking setting of the frequency protection;
[81U1.En] is the logic setting of the stage 1 under-frequency protection;
[81U1.En1] is the binary signal for enabling the stage 1 under-frequency protection;
[81U1.Blk] is the binary signal for blocking the stage 1 under-frequency protection.
3.16.2 Over-frequency Protection
The feeder relay provides a two-stage over-frequency protection with independent definite time delay characteristics, and the two stages have same protection logics.
This protection can be enabled after 100ms only when the frequency is less than the frequency setting [81Ox.f_Set] (x: 1~4) and three phase-to-phase voltages are greater than the setting [81.Upp_VCE]. Meanwhile, this protection will be blocked when the power frequency is less than 35.00Hz or greater than 70.00Hz and this situation keeps for longer than 200ms.
The logic diagram of the stage 1 over-frequency protection is shown as below.
Figure 3.16-2 Logic diagram of the stage 1 over-frequency protection
Where:
[81O1.f_Set] is the frequency setting of the stage 1 over-frequency protection;
“tOF1” is the setting [81O1.t_Op], the time setting of the stage 1 over-frequency protection;
[81.Upp_VCE] is the under voltage blocking setting of the frequency protection;
[81O1.En] is the logic setting of the stage 1 over-frequency protection;
[81O1.En1] is the binary signal for enabling the stage 1 over-frequency protection;
[81O1.Blk] is the binary signal for blocking the stage 1 over-frequency protection.
3.16.3 Frequency Rate-of-change Protection
This relay provides a four-stage rate-of-change of frequency protection with independent definite time delay characteristic, and the four stages have same protection logics.
This relay provides a four-stage rate-of-change of frequency protection with independent definite time delay characteristic, and the four stages have same protection logics.