In total, there are five different types of buses in RX62N microcontroller board. The fol- lowing section lists various bus specifications. It describes whether the bus operates in syn- chronization with a clock or not.
1. CPU bus:
䡲 Instruction bus:
It is connected to the CPU and to the on-chip memory such as on-chip RAM and on-chip ROM. It operates in synchronization with the system clock (ICLK).
䡲 Operand bus:
It is connected to the CPU and to the on-chip memory such as on-chip RAM and on-chip ROM. It operates in synchronization with the system clock (ICLK).
2. Memory bus:
䡲 Memory bus 1: It is connected to on-chip RAM. 䡲 Memory bus 2: It is connected to on-chip RAM.
3. Internal main bus:
䡲 Internal main bus 1: It is connected to the CPU and operates in synchroniza- tion with the system clock (ICLK).
䡲 Internal main bus 2: It is connected to the DMACA, DTC, and EDMAC. Also, it is connected to on-chip memory, namely on-chip RAM and on-chip ROM. It operates in synchronization with the system clock (ICLK).
4. Internal peripheral bus:
䡲 Internal peripheral bus 1: It is connected to peripheral modules and operates in synchronization with the system clock (ICLK).
䡲 Internal peripheral bus 2: It is connected to peripheral modules, on-chip ROM (for programming and erasure), and data-flash memory. It operates in synchro- nization with the peripheral-module clock (PCLK).
䡲 Internal peripheral bus 3: It is connected to peripheral modules (USB) and it operates in synchronization with the peripheral-module clock (PCLK). 䡲 Internal peripheral bus 4: It is connected to peripheral modules (EDMAC and
ETHERC) and it operates in synchronization with the system clock (ICLK). 䡲 Internal peripheral bus 5: It is connected to peripheral modules and it operates
in synchronization with the system clock (ICLK).
䡲 Internal peripheral bus 6: It is connected to on-chip ROM (for programming and erasure) and data-flash memory. It operates in synchronization with the peripheral-module clock (PCLK).
5. External bus:
䡲 CS area: It is connected to the external devices and it operates in synchroniza- tion with the external-bus clock (BCLK).
䡲 External bus SDRAM area: It is connected to the SDRAM and it operates in synchronization with the SDRAM clock (SDCLK).
Description of Buses
1. CPU Buses:
The CPU buses consists of instruction and operand buses, which are connected to internal main bus 1 as shown in Figure 3.17. The instruction bus is used to fetch in- structions for the CPU, while the operand bus is used for operand access. These buses are connected to on-chip RAM and on-chip ROM and therefore the CPU can directly access these areas. Direct access refers to that access which is not by way of internal main bus 1. In contrast to access through internal main bus 1, direct ac-
cess allows only reading the on-chip ROM by the CPU. Programming and erasure are handled by way of an internal peripheral bus. Internal main bus 1 handles bus requests for instruction fetching and operand access. The operand access has a higher priority than instruction fetching. The bus-access operations can proceed si- multaneously, irrespective of whether the instruction fetching and operand access need different buses or not. For example, parallel access to an on-chip ROM and on-chip RAM or to an on-chip ROM and external space is possible.
2. Memory bus:
There are two memory buses; namely memory bus 1 and memory bus 2. On-chip RAM is connected to memory bus 1 and on-chip ROM is connected to memory bus 2. Bus requests from the CPU buses and internal main bus 2 are handled through memory buses 1 and 2. Internal memory bus 2 has a higher priority than the CPU bus.
3. Internal main bus:
The internal main bus consists of two buses; one is internal main bus 1, which is used by the CPU; and internal main bus 2, which is used by the other bus-master modules such as the DTC, DMACA, and EDMAC. Bus requests for instruction fetching and operand access are handled through internal main bus 1. Operand ac- cess has higher priority than instruction fetching. Bus requests from the DTC, DMACA, and EDMAC are handled by internal main bus 2. The order of priority is EDMAC, DMACA, and then DTC, as shown in Table 3.3. The bus access opera- tions can proceed simultaneously. For instance, if the CPU and another bus master are requesting access to different buses; in this case, the respective bus-access op- erations will take place simultaneously. Internal main bus 2 has a higher priority than internal main bus 1. However, when the CPU executes the XCHG instruction, the only request that can access bus is the request from CPU, until and unless data transfer for the XCHG instruction is completed. If data transfer for the XCHG is completed, requests for bus access from other masters will be accepted. Further- more, during reading and writing back of control information, the only bus master which has access is DTC. Bus requests from other masters are not accepted.
TABLE 3.3 Priority of Bus Masters.
PRIORITY BUS MASTER
High Low EDMAC DMACA DTC CPU
Figure 3.17 Bus Configuration.Source: Hardware Manual, Figure 12.1, page 12–2. Peripheral module Peripheral module Peripheral module Peripheral module On-chip ROM Data Flash Memory EXD MAC Peripheral module D M A C A
External bus control Write buffer SDCLK Synchronisation BCLK Synchronisation SDRMAC CSC
Internal main bus 2
BCLK Synchronisation
PCLK Synchronisation
External bus
1: Internal peripheral bus 1 2: Internal peripheral buses 2 and 3 3: Internal peripheral buses 4 and 5 4: Internal peripheral bus 6 1*
2* 3*
4* CPU
DTC DMACA(m) EDMAC Bus error monitoring
section On- chip ROM On- chip RAM ICLK Synchronization Instruction bus Operation bus