A custom built VHDL coded firmware has been implemented, that works seamlessly with the embedded software on the PowerPC through a wishbone architecture and a Peripheral Component Interconnect Express (PCIe) interface. The block diagram of the implemented firmware for the 4DSP FMC108 FMC modules, is shown in Fig. 3.18. As previously discussed, each module provides eight analog to digital converter channels with a sample rate up to 250 MHz. As shown in Fig. 3.18, the eight input channels are synchronized to the internal clocks and fed into a First In First Out (FIFO) architecture. The FIFO is used to pass the radar captured samples from the individual ADC clock domains into the common clock domain for all ADCs, which is run with a 250 MHz clock derived from one of the ADCs. For each ADC data stream, a separate snapshot memory with a capacity of 32768 samples is implemented. The snapshot memories can
Chapter 3. 3D Imaging FMCW MIMO Radar - 24 x 24 - Portable 55
Frequency (GHz)
15
15.5
16
16.5
17
17.5
S-Parameter (dB)
-30
-29
-28
-27
-26
-25
-24
-23
-22
-21
-20
Figure 3.13: Measured maximum coupling between one TX and one RX antenna. The chosen elements were adjacent, with a distance (d) of 15 mm.
be started individually or at the same time, and the start may be synchronized to the external trigger signal. Recording stops when the snapshot memory is full, and the appropriate finish bits are set. The sample memories are accessible at any time from the PCIe bus. The finish condition can be used to generate an interrupt on the PCIe bus.
3.4.2.1 Snapshot Memory
The analogue to digital converters are dual channel models, delivering two channels with a single clock. The two channels are synchronized with the appropriate sample clock, fed through a delay pipeline, which can be individually selected between 1 to 16 register stages, and written to a FIFO, using the AD sample clock. Fig. 3.18 shows the schematic of the ADC input block. For channels one to four, and six, the ADC sample clocks are used to run the input circuitry.
There are eight individual snapshot memories, one for each channel. The wishbone access interface is common to all eight memories, providing one wishbone slave interface internally. Each snapshot memory may be individually started by software, or it may be synchronised to the trigger signal. When the trigger signal is used, a trigger mask selects the channels which are started by the trigger signal, allowing a subset of channels to be used. Control of the snapshot is simple: A start bit (or corresponding trigger mask bit) is used for starting the data recording, and when the memory is full, a finish bit is set for each channel. When the start condition is removed (by clearing the start bit and/or resetting the trigger condition), the finish bit is cleared, and the memory is ready to be started again.
Chapter 3. 3D Imaging FMCW MIMO Radar - 24 x 24 - Portable 56
Pin (dBm)
-14 -12 -10 -8 -6 -4 -2
0
2
4
6
8 10
Pout (dBm)
0
2
4
6
8
10
12
14
16
18
20
Figure 3.14: Measured input power versus output power in the transmitter board. The measurement was performed from the input to the coupler C1 before the antenna.
The effects of the coupler are compensated.
Power and Control Unit Antenna Array FMCW Signal Distribution Board Stacked RX Panels TX Panel TX Panel
Figure 3.15: Photographs of the stacked TX, RX and FMCW signal distribution panels. The left image shows the complete RF front-end unit. The right image is a
section view of its structure.
can be read or written at any time. Writing the memory may be used for debugging purposes, during normal operation it is not required or advisable, since it will interfere with the recording of the samples.
Additionally the snapshot memory provides a clock domain transition to the wishbone clock domain. The latter is used for registers and memory accesses, and provides the connection to the PCIe interface block. Each snapshot memory provides space for 32768 samples (32k). The wishbone interface accesses all snapshot memories of all channels consecutively, providing a memory region of 256k samples. Each sample is provided in a
Chapter 3. 3D Imaging FMCW MIMO Radar - 24 x 24 - Portable 57
RX
TX
RF Frontend
Digital System
Antenna Array Front-View (with Radome)
Antenna Array Front-View: Stacked TX and RX Panels (without Radome)
FMCW Distribution Board
RX
TX
Figure 3.16: Photographs of the complete MIMO radar system. In the upper left image, the integrated RF front-end and digital system is presented. On the lower left
and right images, a front view of the antenna array is shown.
single four byte sized word, sign extended to the full 32 bits. The entire snapshot memory occupies one megabyte of addressable memory on the wishbone and PCIe busses.
3.4.2.2 Clock Distribution Control and ADC Control
The clock management of the 4DSP FMC108 module is implemented using an AD9510 clock management chip [135]. The chip is controlled using a SPI interface [136]. The registers of the chip are presented in a word array of 256 32-bit words. Each 32-bit word allows read or write access to one of the 256 8-bit registers. The underlying SPI protocol is completely implemented in the FPGA firmware, registers are read or written with simple accesses to the appropriate register locations. A single register write will not stall the accessing processor. A subsequent operation will stall until the write has been finished. Read operations stall until the read data value has been obtained from the SPI interface. For high performance operations, processor accesses to the SPI interface should be carefully timed to prevent long processor stalls.
Each ADC chip provides a SPI interface to access internal registers. Each chip offers an eight bit address to select the registers. The registers are mapped to a 32-bit word each, directly accessible on the Wishbone or PCIe bus, respectively. The SPI accesses are handled internally by the FPGA firmware, stalling the accessing processor as appropriate to achieve the access.
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DDS and PLL Power PC
FPGA boards with ADCs
Figure 3.17: 3D illustration of the complete digital unit with the 3 FMC-FPGA boards, the PowerPC and the DDS and PLL board.
Figure 3.18: Schematic overview of the firmware implemented for the 4DSP FMC108 FMC modules.
The access blocks for each ADC are following after each other, and the interface is implemented as a common interface for all four devices. This is necessary since the AD converter chips share the SPI output lines (clock, and data), and only the select and read data lines are separate.
Chapter 3. 3D Imaging FMCW MIMO Radar - 24 x 24 - Portable 59
Figure 3.19: Picture of the MIMO radar control graphic human machine interface (HMI).