Wonjong Kim and Hyunchul Shin have explored a method of hierarchical netlist extraction using an algorithm that performs three main functions: merge series transistors, find simple gates, and match hierarchical subcircuits [12]. In the context of the research conducted by Wonjong Kim and Hyunchul Shin, their concept of levels of hierarchy is equivalent to the concept of levels of abstraction presented in this research.
2.2.1.1 Merge Series Transistors.
The first part of this algorithm is to merge series transistors into a multi-gate device by searching for nets that, for the same type of transistors (either p-type or n-type),
connect only two source/drain terminals. Excluded from the merger, though, are nets that
connect to an external terminal in a larger circuit [12].
2.2.1.2 Find Simple Gates.
The second part of the algorithm is to use the merged series transistors to find simple gates, including inverters, NOR gates, and NAND gates.
For inverters, the algorithm takes into account the fact that inverters are composed of a p-type transistor and an n-type transistor that share a common source/drain signal (the source and drain of a transistor are interchangeable) and gate signal. The other
source/drain signal is connected to Vdd for the p-type transistor and ground (gnd) for the
n-type transistor.
NOR gates are partly composed of p-type transistors in series with n-type transistors in parallel. Hence, when it is identified that there are merged series p-type transistors that have one source/drain connection with Vdd, the algorithm searches for n-type transistors
that a) share a source/drain connection with the merged series p-type transistors and b) share gate connections with the merged series p-type transistors. If the algorithm finds the
n-type transistors that meet the two criteria, the n-type transistors and corresponding p-type transistors are replaced with a NOR gate.
Similarly, NAND gates are partly composed of p-type transistors in parallel and n-type transistors in series. When it is identified that there are merged series n-type transistors and one source/drain connection is gnd, the algorithm searches for p-type transistors that share both a source/drain connection and gate connections with the merged series n-type transistors. If the p-type transistors are found, both the p-type transistors and corresponding n-type transistors are replaced with a NAND gate [12].
2.2.1.3 Match Hierarchical Subcircuits.
The third and chief part of the algorithm is to find subcircuits from the netlist. This is done recursively from the lowest hierarchical level to the highest level since a subcircuit can be identified only after the child subcircuits which compose the parent have been identified. To actually find each subcircuit, a modified version of the SubGemini
algorithm is used first to identify all possible matchable locations of the subcircuit in the layout netlist and second to determine if a subcircuit actually exists at each of the possible locations [12]. To complete the first task, the algorithm sets a key node in the schematic netlist and searches for a candidate vector, which is a set of nodes that potentially match the key node. To complete the second task, each node in the candidate vector is examined to determine which of the nodes in the schematic’s subcircuit graph map to the nodes in the layout graph, such that the nodes from the candidate vector match the key node. To accomplish this, a match between the key node and a node in the candidate vector is assumed and the two nodes are uniquely labeled. Using the two nodes as a starting point, the subcircuit and layout netlists are simultaneously given matching labels only if a valid mapping between the two graphs exists. A subcircuit is positively identified when, for all the subcircuit nodes from the schematic netlist, there are labels that have a perfect match in the layout netlist.
However, there are instances in which a subcircuit can be falsely identified. The algorithm identifies this type of error by comparing the number of candidates in the layout netlist for a subcircuit with the number of subcircuits used in the schematic netlist. If the numbers are not the same, then a subcircuit is declared to be falsely identified and is expanded in the next iteration of the algorithm (the next level of hierarchy) [12].
2.2.1.4 Algorithm Insufficiencies as Applied to DARPA’s Circuit Verification
Efforts.
Unfortunately, the algorithm in [12] is insufficient for application to DARPA’s circuit verification methods. For all intents and purposes, the layout netlist in this algorithm can be considered a revised netlist, and the schematic netlist can be considered the golden netlist. In the previous section, it was mentioned that the correctness of identifying subcircuits is based upon a comparison between the layout (revised) netlist and the schematic (golden) netlist. This method inherently bases its operation on the assumption that the circuit represented by the revised netlist is perfectly equivalent to the circuit represented by the golden netlist. Given that a goal of DARPA’s efforts is to identify circuit layouts that have been modified from the original schematic, an algorithm suitable to achieve this goal must conduct SCR solely on the revised netlist and independently of the golden netlist. The research presented in this paper aims to create a novel algorithm that conducts SCR without referencing a golden netlist so that it is suitable for application to DARPA circuit verification. The next section will discuss the methodology of