DESCRIPCIÓN DE PROGRAMAS RELACIONADOS CON EL EMPRENDIMIENTO Y LA TRANSFERENCIA EN LA UPV:

DBCR2, shown in Figure 2-35, is used to configure data address compare operations. 52–53 IAC4US Instruction address compare 4 user/supervisor mode.

00 IAC4 debug events are not affected by MSR[PR]. 01 Reserved.

10 IAC4 debug events can occur only if MSR[PR] = 0 (supervisor mode). 11 IAC4 debug events can occur only if MSR[PR] = 1 (user mode). 54–55 IAC4ER Instruction address compare 4effective/real mode.

00 IAC4 debug events are based on effective address.

01 Unimplemented in the e200z3 (Book E real address compare), no match can occur. 10 IAC4 debug events are based on effective address and can occur only if MSR[IS] = 0. 11 IAC4 debug events are based on effective address and can occur only if MSR[IS] = 1. 56–57 IAC34M Instruction address compare 3/4 mode.

00 Exact address compare. IAC3 debug events can occur only if the address of the instruction fetch is equal to the value specified in IAC3. IAC4 debug events can occur only if the address of the instruction fetch is equal to the value specified in IAC4.

01 Address bit match. IAC3 debug events can occur only if the address of the instruction fetch ANDed with the contents of IAC4 is equal to the contents of IAC3, also ANDed with the contents of IAC4. IAC4 debug events do not occur. IAC3US and IAC3ER settings are used.

10 Inclusive address range compare. IAC3 debug events can occur only if the address of the instruction fetch is greater than or equal to the value specified in IAC3 and less than the value specified in IAC4. IAC4 debug events do not occur. IAC3US and IAC3ER settings are used.

11 Exclusive address range compare. IAC3 debug events can occur only if the address of the instruction fetch is less than the value specified in IAC3 or is greater than or equal to the value specified in IAC4. IAC4 debug events do not occur. IAC3US and IAC3ER settings are used.

58–63 — Reserved

32 33 34 35 36 37 38 39 40 41 42 43 44 63

Field DAC1US DAC1ER DAC2US DAC2ER DAC12M DAC1LNK DAC2LNK —

Reset All zeros1

1 _{Reset by processor reset p_reset_b if DBCR0[EDM]=0, as well as unconditionally by m_por. If DBCR0[EDM]=1,} DBERC0 masks off hardware-owned resources from reset by p_reset_b and only software-owned resources indicated by DBERC0 will be reset by p_reset_b.

R/W R/W

SPR SPR 310

Figure 2-35. DBCR2 Register

Table 2-18. DBCR1 Field Descriptions (continued)

Table 2-19 describes DBCR2 fields.

Table 2-19. DBCR2 Field Descriptions

Bits Name Description

32–33 DAC1US Data address compare 1 user/supervisor mode. 00 DAC1 debug events are not affected by MSR[PR]. 01 Reserved.

10 DAC1 debug events can occur only if MSR[PR] = 0 (supervisor mode). 11 DAC1 debug events can occur only if MSR[PR] = 1 (User mode). 34–35 DAC1ER Data address compare 1 effective/real mode.

00 DAC1 debug events are based on effective address.

01 Unimplemented in the e200z3 (Book E real address compare), no match can occur. 10 DAC1 debug events are based on effective address and can occur only if MSR[DS] = 0. 11 DAC1 debug events are based on effective address and can occur only if MSR[DS] = 1. 36–37 DAC2US Data Address compare 2 user/supervisor mode.

00 DAC2 debug events are not affected by MSR[PR]. 01 Reserved

10 DAC2 debug events can occur only if MSR[PR] = 0 (supervisor mode). 11 DAC2 debug events can occur only if MSR[PR] = 1 (user mode). 38–39 DAC2ER Data address compare 2 effective/real mode.

00 DAC2 debug events are based on effective address.

01 Unimplemented in the e200z3 (Book E real address compare), no match can occur. 10 DAC2 debug events are based on effective address and can occur only if MSR[DS] = 0. 11 DAC2 debug events are based on effective address and can occur only if MSR[DS] = 1. 40–41 DAC12M Data address compare 1/2 mode.

00 Exact address compare. DAC1 debug events can occur only if the address of the data access is equal to the value specified in DAC1. DAC2 debug events can occur only if the address of the data access is equal to the value specified in DAC2.

01 Address bit match. DAC1 debug events can occur only if the address of the data access ANDed with the contents of DAC2 is equal to the contents of DAC1, also ANDed with the contents of DAC2. DAC2 debug events do not occur. DAC1US and DAC1ER settings are used.

10 Inclusive address range compare. DAC1 debug events can occur only if the address of the data access is greater than or equal to the value specified in DAC1 and less than the value specified in DAC2. DAC2 debug events do not occur. DAC1US and DAC1ER settings are used.

11 Exclusive address range compare. DAC1 debug events can occur only if the address of the data access is less than the value specified in DAC1 or is greater than or equal to the value specified in DAC2. DAC2 debug events do not occur. DAC1US and DAC1ER settings are used.

42 DAC1LNK Data address compare 1 linked. 0 No effect.

1 DAC1 debug events are linked to IAC1 debug events. IAC1 debug events do not affect DBSR. When linked to IAC1, DAC1 debug events are conditioned based on whether the instruction also generated an IAC1 debug event.

43 DAC2LNK Data address compare 2 linked 0 No effect.

1 DAC 2 debug events are linked to IAC3 debug events. IAC3 debug events do not affect DBSR. When linked to IAC3, DAC2 debug events are conditioned based on whether the instruction also generated an IAC3 debug event. DAC2 can only be linked if DAC12M specifies exact address compare because DAC2 debug events are not generated in the other compare modes. 44–63 — Reserved for data value compare control (not supported by the e200z3).