Descripción de tecnologías CMS

In Figures A.1 through A.5, we can now look at the “Dual-Vdd CP” curves. We show

the effect of dual-Vdd architectures on total energy and delay (the x-axis shows Vlow

scaling). Dual-Vdd CP ×1.0 is the case where we do not allow the critical path to

increase in the Vdd assignment algorithm. Dual-Vdd CP ×1.25 is the case where we

allow it to increase by 25%, enabling more energy savings. They are implemented either with transmission gates or gate boosting because of the benefits found in the previous sections.

The “Dual-Vdd CP” curves have a different shape than the other ones: they get

back to the original energy/delay characteristics at very low Vlow, instead of over-

shooting to infinity. At nominal Vdd, we actually have Vlow = Vhigh = Vdd−nominal,

so the Vdd assignment algorithm is able to switch all resources to Vlow without in-

creasing CP. This is shown in Fig. 3.11. Then, as we reduce Vlow, the resources on

the critical path cannot switch to Vlow, they stay at high Vdd, but most of the circuit

consumes a bit less energy, so the energy goes down. As we keep reducingVlow, more

and more resources stay in the Vhigh domain (their delay is farther and farther away

from that of the critical path), until a point where Vlow is so low that no more blocks

can be switched to it and energy starts going back up: more of the circuit is in the Vhigh domain than in the Vlow domain. We eventually get back to the energy level of

Vdd−nominal when no block switches to Vlow.

As we can see from Fig. A.1b at 90 nm and nominalVdd, even though transmission

gates reduce delay by 16%, the dual-Vdd scheme brings it back up to 3.6% overhead

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 90nm bulk Vdd (V) Energy Ratio

comp dyn Vhigh comp dyn Vlow comp leak Vhigh comp leak Vlow route dyn Vhigh route dyn Vlow route leak Vhigh route leak Vlow clock

Figure 3.11: Breakdown of energy components in dual-Vddvoltage sweep (apex2.blif

shown)

power switch (Fig. 3.7a), while the rest is due to the 58% larger tile area (for “Dual- Vdd TG CP _×1.0” compared to “Trans Gate”, not shown in Fig. A.1b). Because it increases the delay above the baseline’s delay, the “Dual-Vdd CP×1.0” point does not

show up in Fig. 3.4b “Base CP_×1.0” at 90 nm: it does not even meet the delay target at nominalVdd. However, we can look at the last four cases of Fig. 3.4: “Dual-Vdd TG

CP _×1.0” is the case where the different techniques are allowed to reduce delay up to the delay set by the “Dual-Vdd TG CP ×1.0” curve, and similarly for the “Dual-

Vdd TG CP ×1.25” case. “Dual-Vdd GB CP ×1.0” and “Dual-Vdd GB CP ×1.25”

correspond to gate boosting instead of transmission gates. At 90 nm, we get 43% energy savings for only 3.6% delay overhead; this is looking at the “Dual-Vdd TG CP ×1.0” curve and the “Dual-VddTG CP ×1.0” delay target in Fig. 3.4b, normalized to

“Base” at nominalVdd. We could also normalize this to “Trans Gate” at nominal Vdd

to isolate the effect of dual-Vdd without the effect of transmission gates: At 90 nm, we

get 49% energy savings for 18% delay overhead. This is close to the 48% reduction in power for 18% increase in delay reported by previous work at 100 nm [76].

Back to normalizing to “Base” at nominal Vdd, we note that the energy savings

90 nm, 66% at 7 nm). For LP/LSTP technology, the dual-Vdd savings are low (3.9% at

22 nm, 0.2% at 22 nm), though they start increasing with the switch to FinFETs: 14% at 14 nm, 16% at 7 nm. Therefore, for LP/LSTP, the reduced headroom we have in reducingVdd (Sec. 3.4.3) does not allow the energy to drop low enough to significantly

offset the Vdd programmability overhead. “Dual-Vdd TG CP ×1.25” reduces energy

further by trading off delay. The best energy we can achieve is shown in “No Delay Target”: this is our min-energy goal.

Even though the dual-Vdd architecture (with transmission gates) shows savings

compared to the baseline case, we observe that it does not help reduce energy more than a single-Vdd architecture with power gating and transmission gates, whether it is

for HP or LP/LSTP processes, older or newer technologies, the min-energy or any of the delay goals. Indeed, even though the “Dual-Vdd TG CP ×1.0” curves in Figures

A.1 through A.5 reduce energy without changing delay as we scale voltage, the “Trans Gate + Power Gate” curves start at a lower delay, so they also get headroom to reduce Vdd (until they hit the delay target). This, combined with the fact that they start at

a lower energy because of the added dual-Vdd overhead, makes them perform about

as well as the dual-Vdd scheme, if not better. This is illustrated in Fig. 3.3b.

Once again, we get similar results and conclusions when using gate boosting in- stead of transmission gates.