Determinar el riesgo residual

This register is used to produce a HIGH level output at the port pins configured as GPIO in an OUTPUT mode. Writing 1 produces a HIGH level at the corresponding port pins. Writing 0 has no effect. If any pin is configured as an input or a secondary function, writing 1 to the corresponding bit in the IOSET has no effect.

Reading the IOSET register returns the value of this register, as determined by previous writes to IOSET and IOCLR (or IOPIN as noted above). This value does not reflect the effect of any outside world influence on the I/O pins.

Table 81. Fast GPIO port 0 Pin value byte and half-word accessible register description

Register name

Register length (bits) & access

Address Description Reset

value

FIO0PIN0 8 (byte) 0x3FFF C014 Fast GPIO Port 0 Pin value register 0. Bit 0 in FIO0PIN0 register corresponds to P0.0 ... bit 7 to P0.7.

0x00

FIO0PIN1 8 (byte) 0x3FFF C015 Fast GPIO Port 0 Pin value register 1. Bit 0 in FIO0PIN1 register corresponds to P0.8 ... bit 7 to P0.15.

0x00

FIO0PIN2 8 (byte) 0x3FFF C016 Fast GPIO Port 0 Pin value register 2. Bit 0 in FIO0PIN2 register corresponds to P0.16 ... bit 7 to P0.23.

0x00

FIO0PIN3 8 (byte) 0x3FFF C017 Fast GPIO Port 0 Pin value register 3. Bit 0 in FIO0PIN3 register corresponds to P0.24 ... bit 7 to P0.31.

0x00

FIO0PINL 16 (half-word)

0x3FFF C014 Fast GPIO Port 0 Pin value Lower half-word register. Bit 0 in FIO0PINL register corresponds to P0.0 ... bit 15 to P0.15.

0x0000

FIO0PINU 16 (half-word)

0x3FFF C016 Fast GPIO Port 0 Pin value Upper half-word register. Bit 0 in FIO0PINU register corresponds to P0.16 ... bit 15 to P0.31.

0x0000

Table 82. Fast GPIO port 1 Pin value byte and half-word accessible register description

Register name

Register length (bits) & access

Address Description Reset

value

FIO1PIN0 8 (byte) 0x3FFF C034 Fast GPIO Port 1 Pin value register 0. Bit 0 in FIO1PIN0 register corresponds to P1.0 ... bit 7 to P1.7.

0x00

FIO1PIN1 8 (byte) 0x3FFF C035 Fast GPIO Port 1 Pin value register 1. Bit 0 in FIO1PIN1 register corresponds to P1.8 ... bit 7 to P1.15.

0x00

FIO1PIN2 8 (byte) 0x3FFF C036 Fast GPIO Port 1 Pin value register 2. Bit 0 in FIO1PIN2 register corresponds to P1.16 ... bit 7 to P1.23.

0x00

FIO1PIN3 8 (byte) 0x3FFF C037 Fast GPIO Port 1 Pin value register 3. Bit 0 in FIO1PIN3 register corresponds to P1.24 ... bit 7 to P1.31.

0x00

FIO1PINL 16 (half-word)

0x3FFF C034 Fast GPIO Port 1 Pin value Lower half-word register. Bit 0 in FIO1PINL register corresponds to P1.0 ... bit 15 to P1.15.

0x0000

FIO1PINU 16 (half-word)

0x3FFF C036 Fast GPIO Port 1 Pin value Upper half-word register. Bit 0 in FIO1PINU register corresponds to P1.16 ... bit 15 to P1.31.

Legacy registers are the IO0SET and IO1SET, while the enhanced GPIOs are supported via the FIO0SET and FIO1SET registers. Access to a port pins via the FIOSET register is conditioned by the corresponding FIOMASK register (see Section 8.4.2 “Fast GPIO port Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010 and Port 1:FIO1MASK - 0x3FFF C030)”).

Aside from the 32-bit long and word only accessible FIOSET register, every fast GPIO port can also be controlled via several byte and half-word accessible registers listed in Table 87 and Table 88, too. Next to providing the same functions as the FIOSET register, these additional registers allow easier and faster access to the physical port pins.

Table 83. GPIO port 0 output Set register (IO0SET - address 0xE002 8004 bit description

Bit Symbol Description Reset value

31:0 P0xSET Slow GPIO output value Set bits. Bit 0 in IO0SET corresponds to P0.0 ... Bit 31 in IO0SET corresponds to P0.31.

0x0000 0000

Table 84. GPIO port 1 output Set register (IO1SET - address 0xE002 8014) bit description

Bit Symbol Description Reset value

31:0 P1xSET Slow GPIO output value Set bits. Bit 0 in IO1SET corresponds to P1.0 ... Bit 31 in IO1SET corresponds to P1.31.

0x0000 0000

Table 85. Fast GPIO port 0 output Set register (FIO0SET - address 0x3FFF C018) bit description

Bit Symbol Description Reset value

31:0 FP0xSET Fast GPIO output value Set bits. Bit 0 in FIO0SET corresponds to P0.0 ... Bit 31 in FIO0SET corresponds to P0.31.

0x0000 0000

Table 86. Fast GPIO port 1 output Set register (FIO1SET - address 0x3FFF C038) bit description

Bit Symbol Description Reset value

31:0 FP1xSET Fast GPIO output value Set bits. Bit 0 Fin IO1SET corresponds to P1.0 ... Bit 31 in FIO1SET corresponds to P1.31.

0x0000 0000

Table 87. Fast GPIO port 0 output Set byte and half-word accessible register description

Register name

Register length (bits) & access

Address Description Reset

value

FIO0SET0 8 (byte) 0x3FFF C018 Fast GPIO Port 0 output Set register 0. Bit 0 in FIO0SET0 register corresponds to P0.0 ... bit 7 to P0.7.

0x00

FIO0SET1 8 (byte) 0x3FFF C019 Fast GPIO Port 0 output Set register 1. Bit 0 in FIO0SET1 register corresponds to P0.8 ... bit 7 to P0.15.

0x00

FIO0SET2 8 (byte) 0x3FFF C01A Fast GPIO Port 0 output Set register 2. Bit 0 in FIO0SET2 register corresponds to P0.16 ... bit 7 to P0.23.

0x00

FIO0SET3 8 (byte) 0x3FFF C01B Fast GPIO Port 0 output Set register 3. Bit 0 in FIO0SET3 register corresponds to P0.24 ... bit 7 to P0.31.

0x00

FIO0SETL 16 (half-word)

0x3FFF C018 Fast GPIO Port 0 output Set Lower half-word register. Bit 0 in FIO0SETL register corresponds to P0.0 ... bit 15 to P0.15.

0x0000

8.4.5 GPIO port output Clear register (IOCLR, Port 0: IO0CLR -

0xE002 800C and Port 1: IO1CLR - 0xE002 801C; FIOCLR, Port 0: