Dimensiones de análisis y categorías de desarrollo para estándares de calidad para programas y

(a) Untuned. (b) Tuned.

Figure 6.16: The result of a Monte Carlo simulation over process and temperature

variations before and after the tuning mechanism. independently.

6.5 Simulation and Verification

Besides the decision for the general structure of the transmitter, the dimensioning of all full custom circuit parts is required to meet a specification that supports multiple standards regarding line codings and transmission channels. This specification mainly results from three settings. The source impedance, the line rate and the equalization capabilities. While the first needs an accurate tuning mechanism, that has to be verified for all process and temperature corner cases, the line rate defines the minimum rise times necessary for the output driver. Equalization can be adapted in the range of the available FIR resolution. As already described in 6.2.4 the minimum granularity is1_/44and a free assignment of segments to all cursors is possible. To assure linear steps the current of one segment has to be in a fixed relation to the other segments. Since all segments are built up identically and the type is only determined by the subsequent series resistor, linearity is achieved by accurate individual segment impedance tuning.

So, the source impedance needs to be tuned accurately for every process/tempera- ture setting, since a mismatch will cause reflections and lead to additional signal disturbance. To verify a correct tuning mechanism and that all corner variations can be compensated a special test bench with four tests has been set up. The first three tests enable only the segments of one segment type and sweep the tuning

Chapter 6 Multi-Gigabit Transmitter

Figure 6.17: The post layout RC extracted core driver differential 20 Gbit/s

output signal against a 50 Ohm receiver over three corner cases (from the top: typical, RC worst, RC best).

code while the output impedance is compared against the nominal resistance. The crossing point provides the optimum setting for every segment type group. In the last test these codes are assigned to the segment types and the final output impedance is measured. The results of a Monte Carlo simulation in fig. 6.16 before and after the tuning mechanism show how process and temperature variations are balanced. Before the tuning mechanism impedance varies from 42.3 to 46.4 Ω, while afterwards there is only a variance of ± 1 Ω for a ± 2 σ normal distribution and an expected value of 50.02 Ω.

An overall verification of a transmitter is only meaningful for in the context of a whole SerDes interconnect, consisting of a transmitter, receiver and a transmission channel, including all capacitive and inductive elements. The dielectric and conductor losses depend on the wires, electrical or optical transmission mediums, backplanes, connectors, package, bonding type, PCB and so on. For this work the assumption has been made, that it has to be distinguished between the output load seen by the driver and the subsequent transmission channel. Regarding the dimensioning of the line drivers they should at least have a reasonable slew rate to reload the output capacitance with the target frequency. The target rate of 20 Gbit/s defines a UI width of 50 ps. To achieve full signal swing, usually the rise times should be better than 50 % of one UI, respectively 25 ps in all corners. This

6.5 Simulation and Verification

(a) FIR off (b) FIR on

Figure 6.18: Eye measurement of the transmitter output running a PRBS-31

pattern at 10 Gb/s with disabled and enabled equalization. sets hard requirements on the output driver and all previous circuitry while trying to minimize the power consumption. Furthermore, the low pass characteristics of the output capacitance can also be compensated by appropriate equalization settings. In a first approximation the final dimensioning has been determined by post layout simulations. For this the whole full-custom transmitter circuit has been RC extracted, while most capacitance is added by the output driver node itself, the series termination resistors, the connecting metal traces, the ESD diodes and the pad. The output signals of the simulation are depicted in fig. 6.17 for three different corners. Differences regarding the rise times are traced back to the fact, that different supply voltages are used and different driver tuning settings. As already mentioned, the overall verification is very difficult and only meaningful in the context of a whole SerDes interconnect. The elaborated performance analysis and verification, especially of the FIR filter, has been done using a budgeting procedure, in which the impact of is estimated by special algorithms for the developed real-number models. This budgeting procedure and the related algorithms are presented in [94]. For the results also be kindly referred to this thesis. In addition to the data path related challenges of a transmitter, also the clock sources and the clock distribution are very complex circuits which take much design effort. The research and development of these topics in the context of the OpenMGT project have been examined in [68].

Since the manufactured ASIC just arrived during the completion of this thesis, some first measurements could be made. An eye measurement of the transmitter output signal, running at 10 Gb/s a PRBS-31 pattern is depicted in fig. 6.18.

Chapter 6 Multi-Gigabit Transmitter

Figure 6.19: The core driver full-custom layout built-up of the retime stage and

the two pseudo-differential output buffers.

While in the first picture (a) the FIR is disabled, and all segments drive the same value, in the second picture (b) the FIR is enabled, resulting in significantly more eye-margin. The channel attenuation is higher at the estimated data rate of 20 Gb/s, thus a prospective comparison at that speed will show even more contrast.