DISCUSIÓN – ANÁLISIS DE LOS RESULTADOS

In this thesis, we have explored the implementations of the Harris corner detection algorithm in both hardware and software, specifically we have implemented the algorithm in C and Verilog HDL. The use of LIDE framework makes the prototyping of DSP in software and hardware faster, in my thesis work, LIDE-C and LIDE-V were used for prototyping the algorithm.

DICE, as a complementary environment for experimenting of dataflow modeling of DSP under Linux, makes management and development of DSP models in software and hardware easier. DICE was used throughout my thesis preparation. The handy utilities for switching between different directories, copying and pasting, improve the efficiency of carrying out tedious work under Linux.

LIDE is a highly regular framework. The problem with prototyping DSP systems in hardware is that a testbench is required when we create a Design Under Test (DUT). Creating a testbench is usually more time-consuming part as it requires thorough understanding of how a DUT works. In general, we need to create a testbench for each DUT. In this thesis work, by taking advantage of the framework’s regularity, we wrote a Python script which can generate all templates and testbenches. The code generation mechanism allows us to focus on DUT and swiftly prototype any sort of DSP. The overhead is that: to capitalize on the regularity we need to get to know the regularity, i.e., get to know how to prototype DSPs in LIDE. The design of an actor can be complicated, as we have seen in the design of inter-actor resource-sharing graph.

Digital image processing, as a separate branch from digital signal processing, is crit- ical in modern day DSP systems. The implementations of digital image processing systems can be challenging as we impose more and more constraints. Corner de- tection is an important task in digital image processing, and it is widely used in feature detection, pattern recognition, etc. The algorithm proposed by Harris and Stephens in 1988 is widely used for corner detection. In Verilog HDL implementa-

6. Conclusions and future work 43 tions of the algorithm, different orders of unfolding were applied for Gaussian actors and non-max suppression actor. Unfolding, also called loop unrolling in software engineering, is a technique for increasing performance of a DSP system. In the context of hardware design, unfolding basically means throwing more hardware for computation. The direct impact is that more operations can be done in parallel. In our case, unfolding means more multiplications and comparisons are carried out. It was found out that unfolding for non-max suppression actor not only increases the throughput (performance) of the actor, but also decreases resource usage on FPGA. Unfolding for Gaussian actors, by contrast, increases the use of DSPs on FPGA while decreases FFs to some extent.

All in all, this thesis work has explored different architectures of the Harris algorithm. We have demonstrated the great advantage of using LIDE, we have created 12 implementations of the algorithm in Verilog HDL. In the future, we can have different architectures for each actor in the dataflow graph. By piecing together actors of different architectures, we have different implementations of the algorithm.

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