Figure 95: Slat PSU Installation
FLAP ACTUATORS GENERAL DESCRIPTION
The Flap actuators provide the actuation force to extend and retract the Flap panels on the trailing edge of the wing. There are two Flap panels on each wing with two Flap actuators to each panel to position the panel and carry the actuation loads.
The Flap actuators convert the rotary output motion of the Flap power drive unit through the Flap system driveline to linear motion through a gearbox and ballscrew assembly to move the Flap panels. The actuator gearbox housings are clevis mounted to brackets on the rear wing spar. A mono-ball type bearing in the clevis mount allows for angular displacement of the actuator during operation. A through shaft passes through the gearbox, allowing for the actuator to transfer driveline torque and rotation to the next actuator, or in the case of the most outboard actuator, to the PSU. The gearbox ratio for input to output is 8.5:1.
The Flap actuators convert input rotary motion through a bevel gear drive and a worm gear drive into linear motion via a ballscrew. A wrap spring type input torque limiter is employed for jam failure cases. The gearboxes are of a sealed, non-vented design and a fixed amount of grease is used internally to reduce tare losses at extremely cold temperatures.
The ballscrew assembly is a translating ballnut design with the ballnut attached to the flap panel fitting through a pair of trunnion and pillow block mounts. This mounting arrangement also allows for angular displacement during operation. The rotating ballscrew shaft is fixed linearly in the housing and the ballnut (which is restrained from rotating) translates along the shaft when the ballscrew shaft is rotated. Multiple ball circuits are utilized to prevent open actuator failures caused by failure of one ball circuit. Non-jamming over travel stops are also provided. Torque and rotation from the driveline is transferred from the through shaft to the bevel gearset via the torque limiter/no-back mechanism. The bevel gearset provides torque to the worm and wheel gearset through a drop box arrangement to drive the ballscrew. The drop box provides offset between the
driveline and ballscrew centerlines for installation and kinematic purposes.
-Flap Actuator Torque Limiter/No-Back
Each Flap actuator contains a torque limiter/no-back mechanism to protect the aircraft structure in the event of a jam, and prevent backdriving of the actuator and Flap panels in the event of a driveline disconnect. The torque limiter/no-back consists of two logarithmic tape brakes (torsional wrap springs) installed on either side of the input bevel gear. When expanded the tape brakes engage the inside diameter of the housing sleeve causing torque to be reacted into the actuator housing and aircraft rear spar. One brake acts as a torque limiter in the clockwise direction and a no-back in the counter clockwise direction. The other brake acts as a torque limiter in the counter clockwise direction and a no-back in the clockwise direction. Torque is transmitted from the actuator through shaft to the input bevel gear through a sliding collar that has helical (ramped) surfaces engaging the bevel gear. The sliding collar and bevel gear helical surfaces incorporate torsional backlash and are preloaded together axially using a helical spring. The angles of the helical surfaces are different for clockwise and counter clockwise rotation to provide different torque limiter settings for extend and retract directions. Under static load conditions the no-back mechanism is engaged to prevent aerodynamic panel loads from backdriving the actuator. Output torque from the ballscrew and worm gear set expand the tape brake to prevent rotation of the actuator input shaft. Rotation of the input shaft in response to PDU and driveline commanded movement unlocks the no-back by means of the backlash between the sliding collar and input bevel gear allowing actuator movement in the commanded direction. In the event of a driveline disconnect the no- backs in the Flap actuators outboard of the failure will prevent aerodynamic loads on the panel from backdriving the Flaps into an unacceptable asymmetric condition. The SF-ACE will detect asymmetry of the wing tip position sensors and shut down the Flap system within the maximum allowable asymmetry limits.
In the event of a jam failure case at the actuator station, the actuator input torque will increase above a predetermined set point established by the helical spring and helical surfaces of the sliding collar and bevel gear. The high input torque causes axial movement of the sliding collar against the helical spring and differential rotation relative to the bevel gear. Differential rotation between these two parts causes the tape brake to expand resulting in additional input torque to be reacted into the actuator housing and rear spar structure rather than the worm gear set and ballscrew. The torque limiter therefore limits the maximum output force that can be delivered to the Flap track mechanism and Flap panels.
Figure 97: Flap Actuator Trip Indicator Components -Flap Actuator Torque Limiter Trip Indicatior
A spring-loaded trip indicator, similar to that used on the slat actuator, provides indication of a system torque limiting event and shutdown. This indication aids in troubleshooting and isolation, since the torque-limiting device disengages and resets when the cause of torque is removed and/or the system is reversed. The trip indicator is actuated by axial movement of the torque limiter sliding collar. The trip indicator consists of a torsional spring external to the actuator that is held in place by a shoulder on the trip indicator housing. Axial movement of the sliding collar of the torque limiter presses against a trip indicator pin that pushes the external torsional spring off the housing shoulder. The trip indicator pin is sealed to prevent ingress of moisture. The trip indicator spring can only be reset manually by the mechanic.
To reset the torque limiter trip indicator, rotate the spring in a clockwise direction until the spring snaps into the recess of the indicator housing at the "set position".
Figure 98: Flap Actuator Cross Section Worm Gear
Input Shaft
Torque Limiter/ No- Back
Torque Limiter Trip Indicator
Bevel Gearset/ Dropbox
Wrapped in opposite directions
Figure 99: Flap Actuator Cross Section Thru Ballscrew Forward Attachment Worm Gear Ballnut
Ballscrew Drive
Parameters
The following table defines the gearbox parameters for the various actuator configurations:
Flap Position Gearhead Angle Gear Ratio
Inboard #1L +28.2 deg 8.5:1 Inboard #1R -28.2 deg 8.5:1 Mid #2L 90 deg 8.5:1 Mid #2R 90 deg 8.5:1 Outboard- #3L , #4L -19.0 deg 8.5:1 Outboard- #3R, #4R +19.0 deg 8.5:1
Torque Limiter Settings
The torque limiter, under dynamic conditions, limits the maximum pass-through torque. Each actuator is tested to verify that the torque limiter setting is within the following range:
Extending Retracting Inboard- #1L, #1R 6348 - 12696 N 3607 – 7935 N Mid- #2L, #2R 10934 – 19681 N 5591 – 12301 N Outboard- #3L, #4L, #3R, #4R 13594 – 24468 N 6951 – 15293 N
FLAP OUTBOARD SKEW SENSOR GENERAL DESCRIPTION Electronic skew sensors are located on the Flap system outboard panel to detect and annunciate excessive panel skew in the event of a disconnect of the Flap actuator or drive carriage.
Four dual channel resolvers are used on the two driven Flap carriages for the outboard Flap panels on each wing. The resolvers are attached to the fixed Flap track and are driven by a linkage connected to the Flap carriage. The skew sensors are electrically inter-connected such that differential movement between the two sensors mounted on each end of the same panel is monitored by the Slat/Flap ACEs. In the event that the differential movement detected by the skew sensors exceeds a predetermined acceptable limit the SF-ACEs will shut down the flap system and annunciate the fault. Each SF-ACE monitors one channel of the dual channel resolvers on the left and right hand wing.
The skew sensors have an integral electrical connector which mates with the aircraft wiring harness to interconnect the two sensors to the corresponding SF-ACE channels.
The Flap outboard skew sensors consist of two dual channel resolver units connected to the Flap track carriages at Flap tracks #3 and #4. The primary coil of the resolvers on track #3 is excited by the SF-ACE Flap channel 1. The secondary coils of this resolver are electrically connected to the secondary coils of the resolver on track #4. The excitation coil of the resolver on track #4 (receiving resolver) is the skew sense output connected to the Flap channel of SF-ACE 1. This interconnection forms one channel of skew sensing by providing an electrical signal to the SF-ACE 1 that is proportional to the differential motion between the two skew sensors on that panel. The remaining resolvers in both units are also electrically connected in the same manner and interfaced with the Flap channel SF-ACE 2 resulting in a dual channel architectecture for each outboard panel. Thus each of the two SF-ACEs independently implements skew sensing for each of the outboard Flap panels (left and right hand wings).
As the Flap is extended or retracted by the actuation system, the Flap carriage drives the skew sensor linkage causing rotation of the skew sensor shaft. The difference in the instantaneous angular position of the two resolver shafts (and hence the flap panels) produces a proportional change in the sensed voltage of the reciever resolver. If the difference exceeds a predetermined threshold (either plus or minus), the SF-ACE will shutdown its channel of Flaps and engage the PDU brakes.
SF-ACE 2 performs the same function on the same panels using the other channels of the resolvers. The dual channel approach allows for dispatch of the aircraft with a single slat channel active or a single skew sensor channel failure. Flap panel skew results in the Flap system being failed with “Flap Fail” annunciated.
Mechanical rigging of the flap skew sensors is not required. The Flap skew sensors and linkage arrangement are preset (timed) to provide proper rigging upon installation. Electrical rigging of the Flap
skew sensors will be performed by the SF-ACEs.
Figure 104: Flap Outboard Skew Sensor Installation
SYSTEM BUILT IN TEST AND MONITORING
This section describes the type of failure monitoring used in the system and provides the extent of coverage provided by the various types of monitoring used.
In these subsections the testing discussion focuses on a single SF- ACE channel with differences between slat and flap channels indicated as required. In discussions regarding control and monitor microprocessors, the specific differences between the dissimilar control and monitor software are not addressed; dissimilar software discussion is documented in SF-ACE Architecture/Functional Design.
-Automatic Built-in Test
Auto Built-in Test consists of Power Up BIT, Warm Start, Cold Start, Microprocessor Circuits, Discrete Input Interfaces, Initiated Bit, Motor Tests, Brake Tests, Brake Drive Tests, Continuous Bit, Manually- Initiated Test, Failure Monitoring, and Fault Isolation BITE.
-Power Up BIT
There are two power interruption conditions which affect how Power Up BIT functions in the SF-ACE. If the power interruption is momentary (less than 50 ms), the Power Up BIT performs a warm start. If the power interruption is extended (greater than 50 ms), the Power Up BIT performs a cold start.
Power up BIT latency is approximately 3 seconds for either a cold or warm start when WOW is inactive (aircraft in air). When cold start is performed with WOW active (aircraft on ground) the latency is 30 seconds (actual latency is less, the 30 seconds assures ARINC data integrity).
The SF-ACEs do not transmit ARINC data during the power up BIT. SF-ACE outputs are inactive during the power up BIT.
-Warm Start
Performed when power interruption is less than 50 ms.
In a warm start, each of the microprocessors performs the Application area PROM Checksum Test. If the test is successful, the microprocessors initialize themselves and become operational. -Cold Start
Performed when power interruption is greater than 50 ms. -Microprocessor Circuits (Cold Start)
Each of the microprocessors (control and monitor) performs Boot area PROM checksum, Application area PROM checksum, RAM read/write addressing test, and a Watchdog Timer/FNR test. These are tests to verify the integrity of the microprocessors and their circuitry. The software performs a fail-safe shutdown when any of these tests fail.
-Microprocessor Protection Circuits (Cold Start)
The control microprocessor performs a Fail-safe Shutdown Test, a Monitor Shutdown Output Test, a Power Monitor Circuit Test and a Power Interrupt Monitor Test. These are tests of the microprocessor support hardware and software to verify integrity of the microprocessor protection. The software performs a fail-safe shutdown when any of these tests fail.
-Discrete Input Interfaces (Cold Start)
The control microprocessor stimulates the interface circuits for the SFCS external discrete inputs and subsequently checks the integrity of the values returned. These tests verify the integrity of the interface circuitry for the input discretes for controller address, slat disconnect sensor circuit, and the RAT mode discrete. These tests take approximately 130 ms plus read verification time. Failure of any of these tests is indicated.
-Initiated Bit (Cold Start)
Initiated BIT is performed to cover system LRU faults, which may be dormant due to system redundancies, as described in the following subsections. During initiated BIT, SF-ACE critical system outputs which are not included in the test coverage are held in an inactive state, and test status is indicated over the EICAS interface by setting
SF-ACE ARINC data transmit SSM values to “Functional Test”. Continuous BIT monitoring is active during the initiated testing and the results of continuous monitoring may be used as part of the initiated BIT.
Initiated BIT is performed automatically on a once daily schedule based on the ARINC 429 Date and GMT inputs to the SF-ACE. Initiated BIT can also be commanded via the CMC interface.
Initiated BIT will be inhibited or aborted whenever any of the following conditions exist:
- The WOW signal is inactive or indicates that the aircraft is 'in air',
- Airspeed is greater than 50 knots,
- Any valid slat or flap command is received by any means. - Initiated test abort command from CMC is received (if test
was initiated by CMC command). - AC power is not available.
- Any of the following sensor validity groups indicate invalid: IOBUS, ADC, Left Resolver, Right Resolver, Motor Resolver, SF-ACE ID discretes, Brake torque discretes.
Initiated BIT includes logic for the two opposite channels (two flap channels or two slat channels are referred to as opposites) to communicate via the cross channel bus to prevent both channels from conducting simultaneous motor and brake testing and to allow for test initiation when one channel is not operating, powered, or is in a fail-safe condition.
Both SF-ACEs are subjected to initiated BIT testing per the above criteria. Approximately 150 seconds is allowed for the initiated BIT test to be completed for both SF-ACEs. If the SFCL is moved during
the initiated BIT testing, the test is suspended and any valid commands are executed. In the event the initiated BIT sequence is interrupted at the first flight of the day, the SF-ACEs will attempt to run initiated BIT at every cold start when WOW and CAS <50 knots are valid, until the initiated BIT is run completed.
-Motor Tests
The SF-ACE initiated BIT conducts Regen Test to verify the integrity of the motor regeneration circuit, Switch Test to verify integrity of the motor drive module switches, and Continuity Test to verify the motor windings continuity.
In event of the failure of any of the motor tests, the control processor will disable the motor drive and halt initiated BIT testing. If the motor tests are passed, the control processor will disable the motor drive and continue initiated BIT testing.
-Brake Tests
The brake drive tests are performed in a sequence allowing the reduction of ambiguity to allow isolation to the brake wiring/coils to the extent possible. The brake torque tests are intended to verify the functional integrity of the brake circuitry as well as the brake torque capability.
-Brake Drive Tests
The initiated BIT logic first checks for a brake enable short circuit by monitoring current and voltage in the brake enable with the individual brake drive switches and the brake enable switch open. If a short is indicated the brake drive test is terminated, and initiated BIT is aborted.
If no brake enable short is detected, the brake enable switch is closed while the individual brake drive switches are left open. This condition allows checking for brake enable open testing, positive 28 Vdc to ground testing on the brake enable, checking for individual brake drive switch shorts (left, right and motor), and checking for brake coil circuit opens (left, right and motor). If any of these tests are failed, the brake drive test is terminated and initiated BIT is aborted.
The individual brake switches are then closed and opened one at a time via brake release and engage commands. While each switch is closed, current and voltage are monitored to determine whether the affected brake drive circuit has an open condition and whether or not the brake coil is shorted. This test is completed for Slat and Flap motor brakes. If any of these tests are failed, the brake drive test is terminated and initiated BIT is aborted.
If the initiated BIT successfully completes these brake drive tests and no failures are indicated, all brake commands are removed and the initiated BIT continues.
-Brake Torque Tests
Once the motor and brake drive tests are completed and no failures have been indicated, the initiated BIT performs the brake torque tests to isolate the PDU (including brake), and disconnect failures that may exist.
The control processor will enable the brake drive and the motor drive and then wait 100 ms. before performing the following tests. The control processor shall perform all steps of this test and retain all intermediate results for fault isolation after all steps are complete.
The following parameters, used for these tests, are defined here for Slat and Flap:
Parameter Slat value Flap Value
Current Ramp Rate (Motor) 23.0 A/sec. 23.0 A/sec. PDU Max Current 23.0 A 23.0 A Res Move Limit 4.30 deg. 2.45 deg. Res Move Time 0.03 sec. 0.03 sec. Motor Move Limit 2000 RPM 2000 RPM Motor Move Time 0.55 sec. 0.55 sec. BTS Min Current 2.4 A 2.9 A BTS Min Time 0.03 sec. 0.03 sec.
For the PDU brake torque check, the motor current is ramped up to 23.0 amps and then held for 4.0 seconds. If the motor movement is equal to or exceeds 2000 RPM for 0.55 seconds, the test is terminated immediately. If either wingtip resolver position moves more than the resolver move limit amount (see table above) in 0.03 sec the test will be terminated immediately.
For the PDU brake torque test, the brake circuit switches are set to