Discusión y conclusiones

This section describes the main codes used for encoding the states of an FSM.

The most common encoding alternatives are sequential (also called binary ), Gray , Johnson , and one-hot , all illustrated in fi gure 3.9a for an eight-state FSM. Note that the fi rst two require three bits, the third requires four bits, and the last one requires eight bits.

To illustrate the encoding options further, let us consider a machine with the fol-lowing fi ve states (using VHDL notation):

type state is (A, B, C, D, E);

3.7.1 Sequential Binary Encoding

The states are encoded using the conventional binary code (increasing order of cor-responding decimal values; see fi gure 3.9a ). For the type state above, three bits would be needed, resulting A = “ 000 ” (decimal value = 0), B = “ 001 ” (= 1), C = “ 010 ” (= 2), D = “ 011 ” (= 3), and E = “ 100 ” (= 4).

The advantage of this encoding is that it requires the smallest number of fl ip-fl ops;

with N fl ip-fl ops ( N bits), up to 2 ^N states can be encoded. The disadvantage is that it might require more combinational logic than other encoding options (illustrated in exercises 3.2 and 3.3), so the resulting circuit might be slightly slower.

Figure 3.9

(a) Main encoding options for an eight-state machine. (b) Regular sequential binary counter with outputs converted to Gray code. (c) Johnson counter. (d) One-hot counter.

50 Chapter 3

3.7.2 One-Hot Encoding

At the other extreme is the one-hot code, in which only one bit is high in each code-word, so with N fl ip-fl ops only N states can be encoded (see fi gure 3.9a ). For the type state above, fi ve bits would be needed, resulting in A = “ 00001 ” , B = “ 00010 ” , C = “ 00100 ” , D = “ 01000 ” , and E = “ 10000 ” .

This code demands the largest number of fl ip-fl ops, but the amount of combi-national logic tends to be smaller than that of other encodings (illustrated in exercise 3.2), often leading to a slightly faster implementation. For big machines (say, over 40 or 50 states), the hardware for this type of encoding tends to be prohibitively large.

Just to illustrate the one-hot code, fi gure 3.9d depicts a one-hot counter, which consists simply of a shift register with a direct feedback loop. Note that the initial state is q 3 q 2 q 1 q 0 = “ 0001 ” because the reset signal is connected to the reset port of three DFFs and to the preset port of the other.

3.7.3 Johnson Encoding

This is an implementation in between the two above. With N fl ip-fl ops, 2 N states can be encoded (see fi gure 3.9a ). It does not require much more combinational logic than the one-hot alternative, but it can encode twice the number of states. Each codeword is obtained by circularly shifting the previous codeword to the left and inverting the incoming bit. For the type state above, three bits would be needed, resulting A = “ 000 ” , B = “ 001 ” , C = “ 011 ” , D = “ 111 ” , and E = “ 110 ” .

Just to illustrate the Johnson code, a Johnson counter is depicted in fi gure 3.9c , which consists simply of a shift register with an inverter in the feedback loop.

An important property of this code is that the Hamming distance (number of bits that are different) between any two adjacent codewords is just 1 (see fi gure 3.9a ), so it can be useful in the same applications as the Gray code, described below.

3.7.4 Gray Encoding

Gray code is similar to the sequential code in the sense that it too requires the least number of fl ip-fl ops (with N fl ip-fl ops, up to 2 ^N states can be encoded), but the amount of combinational logic can be slightly larger (illustrated in exercise 3.3) and the speed slightly lower.

This code too exhibits the property of unitary Hamming distance between any two adjacent codewords, useful in certain implementations involving multiple clock domains (recall comments of section 2.3). Because of this property, a Gray counter is free from glitches during state transitions (except when returning to the initial state if the counter ’ s modulo is not a power of 2); consequently, if a Gray-encoded FSM has a long path without branching, transitions along that path are glitch-free.

Hardware Fundamentals—Part II 51

In a Gray code, each codeword is obtained by modifying the value of the rightmost bit in the previous codeword such that a new codeword results (see fi gure 3.9a ). For the type state above, three bits would be needed, resulting in A = “ 000 ” , B = “ 001 ” , C

= “ 011 ” , D = “ 010 ” , and E = “ 110 ” .

Just to illustrate the Gray code, a Gray counter is presented in fi gure 3.9b , which consists simply of a regular sequential counter whose output is converted into Gray code by means of the following expressions (see XOR gates in fi gure 3.9b ): q(N − 1 ) ^Gray

= q(N − 1 ) Seq ; q(i) Gray = q(i +1 ) Seq ⊕ q(i) Seq for i = N − 2 to i = 0.

3.7.5 Modifi ed One-Hot Encoding with All-Zero State

Figure 3.10a shows an example using the true one-hot code described above for a four-bit system (a four-state FSM). As expected, the bits of pr_state are { “ 0001 ” , “ 0010 ” , “ 0100 ” , “ 1000 ” }. A modifi ed version, with bit zero inverted, is depicted in fi gure 3.10b . The encoding is now { “ 0000 ” , “ 0011 ” , “ 0101 ” , “ 1001 ” }, thus containing the all-zero codeword. This code has the same properties as the true one-hot code in the sense that it too has a Hamming distance of 2 between any two codewords, and all code-words can be identifi ed based on a single bit.

The alternative of fi gure 3.10b is used, for example, by Altera ’ s Quartus II compiler when synthesizing state machines using the one-hot option. The reason for doing so is that all DFFs in Altera ’ s FPGAs (and Xilinx ’ s as well for that matter) are initialized to a low output on power-up, so if an explicit reset port was not included in the design, the machine will still be able to start from a specifi c state, avoiding improper initial-ization and deadlock. More details on this are seen in sections 3.8 and 3.9, which discuss the importance of reset in FSMs and how to implement safe FSMs.

Figure 3.10

(a) True one-hot encoding. (b) Modifi ed one-hot encoding (bit zero inverted), containing the all-zero codeword.

52 Chapter 3

3.7.6 Other Encoding Schemes

Besides the encoding schemes described above, VHDL and SystemVerilog synthesis compilers have at least two other options, known as user and auto . The former is a user-defi ned encoding (the codeword for each state is specifi ed by the user), whereas the latter is used to let the compiler choose the best encoding scheme based on the target device. Typically, auto employs sequential encoding for small machines (for example, up to four or fi ve states), then one-hot for medium-sized machines (for example, up to 40 or 50 states), and fi nally sequential again (or an equivalent, such as Gray) for larger machines. In general, auto is the compiler ’ s default option.

The one-hot style is common in applications where fl ip-fl ops are abundant, such as fi eld programmable gate arrays (FPGAs), whereas minimal-bit encodings (such as sequential and Gray) are common in complex programmable logic devices (CPLDs) and in compact, low-cost application-specifi c integrated circuits (ASICs).

Chapters 6 and 7 show how to select the encoding scheme when using VHDL or SystemVerilog, respectively.