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The purpose of this section is to better understand the pole interactions between the inner current control loop and the outer voltage control loop. So far, the inner loop dynamics was approximated as a simple first order delay TF as in [137]. A second order TF will be used here instead, which will reflect the second order CLP position of the inner current loop controller. The transfer function approximations of difference components in the voltage control loop are shown in Figure 4.13. This simplified block diagram is representative for both d and q axes if the interactions between them are assumed to be fully decoupled.

Controller PI Lead Dynamics/Delay Dynamics τzs + 1 τps + 1 G (s − p)(s − p∗₎ Kp+ Ki s 1 Cs e u i v vref iref Compensator

Current Inner Loop Capacitor

Figure 4.13: Simplified control block diagram of the dq voltage controller with transfer functions.

Figure 4.14 shows the root locus plots and closed loop pole (CLP) positions for three difference cases, represented by different colours. The root locus is the tra- jectory of the CLPs as the gains in voltage control feedback loop is varied. The plot is found using the root locus (rlocus) command in MATLABr with the rele- vant transfer functions put together as the system. The CLPs are found using the feedback command to generate the closed loop TF and then the pzmap command is used to map out the pole locations, which are represented by the square symbols. The same PI control gains that were calculated using the place method as described in Section 4.3.4 were included to find the CLP for each case. The inner-outer loop speed ratio used here is ωni1/ωno1 = 2.5, and the damping factor and inner current

loop base speed remains the same as previously discussed.

The original gain calculation method used assumed that the current inner loop control response is instantaneous. If the assumption was true, the expected root locus and CLP is represented in blue as the ‘ideal case’, shown in Figure 4.14.

The root locus and CLPs for the ‘no compensation case’ are shown in black, which is where the closed loop response poles of the inner loop (current control CLP) are taken into account in the transfer function model. In comparison with the ‘ideal case’, it shows how the root locus of the voltage control loop for the ‘no compensation case’ is distorted and the CLP position is displaced further away than intended. The ‘no compensation case CLP2’ is on the root locus leading from the second-order inner loop poles denoted as ‘current control CLP’. It is the ‘no compensation case CLP2’ that repels the ‘voltage control CLP’ towards right hand side towards the unstable region, where the damping is reduced. The chosen control gains for this case seems to be higher than it should be and the margin before it

4.5. Design and Analysis of the AC Voltage Control Dynamics 111 -1400 -1200 -1000 -800 -600 -400 -200 0 200 -200 0 200 400 600 800 1000 1200 1400

Real Axis (seconds-1)

Imaginary Axis (seconds

-1 ) Leading Compensator Zero (τ_z = 0.0009s) Voltage Control CLPs No Compensation Case CLP Compensated Case CLP Ideal Case CLP

(No current delay or compensation) Current Control CLP ζ = cos ϕ = 0.7 PI Control Zero

ϕ

Figure 4.14: Root locus plots and closed loop pole positions of a voltage controller design (ωni1/ωno1 = 2.5) for a case with a leading compensator, a case without one and

an ideal case.

reaches the unstable region is smaller. However, even if the gains are further lowered and the voltage control CLP is moved further down along the root locus, the voltage control action will slow down and the damping will not significantly increase. This is because vector angle of the CLP will still remain quite high, based on the root locus trajectory.

The root locus and CLPs shown in red are for the ‘compensated case’, where a leading zero with a time constant of τz = 0.0009 second is included, which partially

compensates the phase lag of the inner loop current control response. The lagging pole that is usually paired with this zero is ten times further away and therefore has little impact on the area of interest. There should be four CLPs in this‘compensated

case’, but only two are shown as Figure 4.14 is cropped, and only showing mostly the top half of the plot. This is mirrored along the the <eal-axis, at =m = 0, for the conjugates at the bottom half. The ‘voltage control CLP’ of interest for the ‘compensated case’ seem to be reasonably close to the CLP positions for the ‘ideal case CLP’.

The angle of the compensated voltage control CLP is slightly lower than the designed target damping angle φ = cos−10.7, therefore this particular CLP is slightly more damped. However, the angle of the ‘compensated case CLP2’, on the root locus trailing from the ‘current control CLP’ position, is greater than the reference angle for ζ = 0.7. The root locus from here is projected towards the top right hand side, which is why the minimum damping will always be less than the designed damping of the inner loop current controller. The magnitude does not significantly change, so its natural frequency response speed is maintained. The damping factor of 0.35 for the ‘compensated case CLP2’ matches quite closely with minimum system eigenvalue damping in Figure 4.12 (approximately 0.37 at ωni1/ωno1 = 2.5). By increasing

the damping of the ‘current control CLP’, it may be possible shift the root locus starting position for the ‘compensated case CLP2’ to a lower position with increased damping as well.