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You can set the following properties using either of the following methods:

Project Navigator: Map Properties operations with user-generated timing constraints. B default, the Map Effort Level is set to Medium when usin Perform Timing-Driven Packing and Placement. Howeve setting the Map Effort Level to High ( map -ol hig achieves the best results. With this setting, your Ma runtime increases. This combination creates a fully place but not routed NCD file.

Note When running place and route, you do not  need t set the Place and Route Mode to Route Only or use th par -p option. Place and route does not redo placement.

Map to Inp Functions

-k {4|5|6|7|8} Use this property to reduce the levels of logic. Use thi property sparingly and only after you have attempted t reduce the levels of logic in your HDL source file.

Pack I/O Register Latches into IOBs

-pr {i|o|b} Use this property to reduce setup and clock-to-out timin from pad to register or register to pad.

Performance-Related Place and Route Properties

You can set the following properties using either of the following methods:

Project Navigator: Place & Route Properties

Command line: PAR options (For details, see the "PAR Options" section in the "PAR" chapter of the Development System Reference Guide .)

Place & Rout

Effort Lev

(Overall)

-ol {std|med|high} Set this property to High when the design timing objective are aggressive.

Placer Effort Level -pl {std|med|high} Set this property to High when the placement is not optima Router Effort Level -rl {std|med|high} Set this property to High when timing is not achieved b

placement is optimal.

Extra Effort -xe {n|c} Set this property when you are close to meeting timin objectives. Extra Effort is not  recommended as a defau setting. It is not  recommended when you are far fro meeting your timing objectives, because it increase runtimes.

Note In Project Navigator, you can only modify the Extr Effort Level if the Place & Route Effort Level (Overall) is s to High. On the command line, you can only set par -x when also setting -ol high.

Advanced Place and Route Strategies

Following are advanced strategies for placing and routing your design:

Use clock region area groups with time groups as area groups.

Use this strategy on a limited basis when necessary. This strategy is useful in confining the synchronous elements of global clock buffers to specific clock regions to prevent contention in clock regions between global clocks. For details, see the "AREA_GROUP" and "TIMEGRP" sections in the "Constraints" chapter of the Constraints Guide .

Create relationally placed macros (RPMs) to help with packing and placement. For details, see the

"RLOC" section in the "Constraints" chapter of the Constraints Guide .

Use manual routing with directed routing constraints in the FPGA Editor to maintain the routing of critical nets. For details, see Manually Routing your Design in the FPGA Editor Help.

Floorplan your critical path to help in placement and in packing. For details, see the Floorplanner Help.

Use FPGA Editor when necessary, as described in Implementation Strategies using FPGA Editor .

Timing Constraints

Use timing constraints as follows:

Do not overconstrain the design to meet timing objectives.

For example, do not place a 120 megahertz (MHz) constraint on a 100 MHz clock. Overconstraining the design makes it more difficult for the placer and router to achieve timing closure. In some cases,

this produces worse results than using realistic timing objectives. Overconstraining is the most frequent cause of a long place and route runtime.

Use timing constraints in your synthesis tool to get the best possible design implementation.

Use global timing constraints instead of individual timing constraints where possible.

TIMEGRP

Use TIMEGRPs to group signals with the same timing requirements. If a FROM-TO constraint is necessary, define the specific TIMEGRP instead of using generic timing groups, such as FFS and RAMS. This reduces runtime and dramatically reduces memory usage.

OFFSET

Use OFFSET constraints with individual timing groups only for exceptions, for example, when the input or output signals are clocked by the same clock but have different timing requirements.

PERIOD

Use PERIOD constraints whenever possible. Limit the number of FROM-TO constraints.

FROM-TO

Use FROM-TO to define a multi-cycle path that does not require meeting a single cycle. Group as many elements together as possible to limit the number of FROM-TO constraints.

TIG

Use TIG constraints when appropriate to reduce the difficulty of meeting all timing constraints during Place and Route.

Additional Recommendations

Following are additional recommendations to reduce runtime and improve design performance:

Manually place RAMB16 and MULT18X18 design elements to reduce runtime. For details, see the

"LOC" section in the "Constraints" chapter of the Constraints Guide .

Limit the use of AREA_GROUP constraints. Too many AREA_GROUP constraints, especially overlapping ones, cause long runtimes.

Consider using the hierarchical design flows to reduce runtimes when limited changes are made to the design. For details, see Hierarchical Flows Strategies for FPGAs .

Ensure that your computer has twice the amount of RAM listed as used in the Place & Route (PAR) report, up to the maximum of 4 gigabytes (GB). This reduces the possibility of using disk swap space.

Use the PlanAhead® software to reduce runtime and achieve faster performance.