See clause 7 of [ITU-T G.806] for a generic description of information flow. For OTN-specific information flow see the description of the functions in clause 9.
8 Generic processes
Generic processes are defined in clause 8 of [ITU-T G.806]. This clause defines the specific process for the OTN.
8.1 Scrambling processes
Scrambling is required for the OTUk signal. The OTUk scrambler is defined in clause 11.2 of [ITU-T G.709].
8.2 Alignment processes 8.2.1 OTUk frame alignment
The OTUk frame alignment shall be found by searching for the OA1, OA2 FAS bytes (see [ITU-T G.709]) contained in the OTUk frame.
The process has two states, out-of-frame (OOF) and in-frame (IF).
In the OOF state, the framing pattern searched for shall be a 4-byte subset of the OA1 and OA2 bytes. The IF state shall be entered if this subset is found and confirmed one frame period later.
In the IF state, the frame signal shall be continuously checked with the presumed frame start position for correct alignment. The framing pattern checked for shall be the OA1OA2OA2 pattern (bytes 3, 4 and 5 of the first row of the OTUk frame). The OOF state shall be entered if this subset is not found at the correct position in 5 consecutive frames.
The frame start shall be maintained during the OOF state. 8.2.2 OTUk multiframe alignment
The OTUk multiframe alignment shall be found based on the MFAS byte (see [ITU-T G.709]) contained in the OTUk frame.
The process has two states, out-of-multiframe (OOM) and in-multiframe (IM).
In the IM state, OOM shall be assumed when the received MFAS does not match with the expected multiframe number in 5 consecutive OTUk frames.
In the OOM state, multiframe alignment shall be assumed to be recovered, the multiframe counter shall be set to the new MFAS, and the IM state shall be entered, when a valid MFAS sequence is
found in two consecutive OTUk frames. The MFAS sequence is valid if the MFAS of the second frame is the increment of the MFAS of the first frame.
The multiframe start shall be maintained during the OOM state. 8.2.3 ODUj[/i] frame and multiframe alignment
The ODUj[/i] frame and multiframe alignment shall be found by searching for the framing pattern (OA1, OA2 FAS bytes) and checking the multiframe sequence (MFAS byte) (see [ITU-T G.709]) contained in the ODUj[/i] frame.
The process has two states, out-of-frame (OOF) and in-frame (IF).
In the OOF state, the framing pattern searched for shall be the full set of the OA1 and OA2 bytes. The IF state shall be entered if this set is found and confirmed one frame period later and an error free multiframe sequence is found in the MFAS bytes of the two frames.
In the IF state, the frame alignment signal shall be continuously checked with the presumed frame start position and the expected multiframe sequence. The framing pattern checked for shall be the OA1OA2 pattern (bytes 3 and 4 of the first row of the ODUj[/i] frame). The OOF state shall be entered if this subset is not found at the correct position in 5 consecutive frames or the received MFAS does not match with the expected multiframe number in 5 consecutive frames.
The frame and multiframe start shall be maintained during the OOF state. 8.2.4 ODUk virtual concatenation multiframe alignment
The ODUk virtual concatenation multiframe (VCMF) is used on top of the ODUk MFAS multiframe. It uses the MFI1 and MFI2 bytes of the VCOH overhead as defined in clause 18.1.2.2.2.1 of [ITU-T G.709].
The process has two states, out-of-multiframe (OOM) and in-multiframe (IM).
In the IM state, OOM shall be assumed when the received VCMF number in the MFI1 and MFI2 bytes of the VCOH does not match with the expected multiframe number in 3 consecutive ODUk MFAS multiframes.
In the OOM state, multiframe alignment shall be assumed to be recovered, the multiframe counter shall be set to the received VCMF number, and the IM state shall be entered, when a valid VCMF sequence is found in two consecutive ODUk MFAS multiframes. The VCMF sequence is valid if the received VCMF number of the second MFAS multiframe is the increment of the received VCMF number of the first frame.
NOTE – The MFI1 and MFI2 bytes are transmitted eight times per MFAS multiframe, containing the same VCMF number. For the VCMF alignment process, only the first occurrence of the MFI1 and MFI2 bytes in the MFAS multiframe (MFAS multiframe numbers 0 and 1) shall be used. The multiframe start shall be maintained during the OOM state.
8.2.5 Logical Lane Frame alignment
Logical Lane frame alignment shall be found by searching for the OA1, OA2 FAS bytes within the logical lane as specified in Annex C/G709.
The process has two states, out-of-frame (OOF) and in-frame (IF).
In the OOF state, the framing pattern searched for shall be a 4-byte subset of 3 OA1 followed by N OA2 bytes present periodically after every 16320 bytes. The IF state shall be entered if this subset is found and confirmed a period of 16320 bytes later. N=3 for four logical lane (OTU3) interface and
In the IF state, the frame signal shall be continuously checked with the presumed frame start position for correct alignment. The framing pattern checked for shall be the OA1OA2OA2 pattern (bytes 3, 4 and 5 of the first row of the logical lane frame). The OOF state shall be entered if this subset is not found at the correct position in 5 consecutive periods of 16320 bytes.
The frame start shall be maintained during the OOF state.
Note: This process is identical to the OTUk frame alignment process. 8.2.6 Logical lane alignment
The logical lane alignment process is used to establish alignment of the lanes of the OTUk multilane interface.
The bytes of the OTUk signals (k= 3,4) are distributed to the logical lanes in 16-byte increments as specified in Annex C of Recommendation G.709.
For the OTU3 with four logical lanes the MFAS is reused as logical lane marker information. The MFAS sequence 00000000, 00000001, .. , 11111111 (i.e. 0 to 255) is inserted before distribution of the OTU3 bytes over the four logical lanes. After distribution of the OTU3 16-byte increments over the four logical lanes, each lane will carry a subset of the MFAS values of which the two least significant bits are constant ( either 00, 01, 10, or 11) and identifies the logical lane number.
- Logical lane 0 will carry the following MFAS values: 000000 00 – 000001 00 – 000010 00 – 000011 00 – 000100 00 – 000101 00 – … - 111111 00.
- Logical lane 1 will carry the following MFAS values: 000000 01 – 000001 01 – 000010 01 – 000011 01 – 000100 01 – 000101 01 – … - 111111 01.
- Logical lane 2 will carry the following MFAS values: 000000 10 – 000001 10 – 000010 10 – 000011 10 – 000100 10 – 000101 10 – … - 111111 10.
- Logical lane 3 will carry the following MFAS values: 000000 11 – 000001 11 – 000010 11 – 000011 11 – 000100 11 – 000101 11 – … - 111111 11.
For the OTU4 with twenty logical lanes the LLM carries the logical lane marker information. The LLM sequence 00000000, 00000001, .. , 11101111 (i.e. 0 to 239) is inserted before distribution of the OTU4 bytes over the twenty logical lanes. After distribution of the OTU4 16-byte increments over the twenty logical lanes, each logical lane will carry a subset of the LLM values of which the modulo 20 value is constant and identifies the logical lane number.
- Logical lane 0 will carry the following LLM values (0,20,40,60, ..,200,220): 00000000 – 00010100 – … - 11011100.
- Logical lane 1 will carry the following LLM values (1,21,41,61, .., 201,221): 00000001 – 00010101 – … - 11011101.
- …
- Logical lane 18 will carry the following LLM values (18,38,58,78, ..,218,238) : 00010010– 00100110 – … - 11101110.
- Logical lane 19 will carry the following LLM values (19,39,59,79, ..,219,239): 00010011 – 00100111 – … - 11101111.
8.2.6.1 OTU3 multi-lane alignment The process has two sub-processes:
- Multi-lane alignment (composite signal)
The logical lane marker signal is located in bit 7 and 8 of the MFAS byte of the logical lane frame. These bits are scrambled with the scrambler given in clause 11.2 of [ITU-T G.709].
A logical lane marker recovery process is present per logical lane to recover the logical lane marker value. A new value of the logical lane marker is accepted when in five consecutive 16320 byte periods the same value is present in bits 7 and 8 of the MFAS byte, and the recovery process will enter the In-Recovery (IR) state. In the IR state, recovery will be lost and the Out-of-Recovery (OOR) state be entered, when in each of five consecutive 16320 byte periods a value is received that is not the same as the accepted logical lane marker value. During an OOR period, the last accepted LLM value has to be maintained as lane marker value.
If the Logical lane marker recovery process is in the out-of-recovery (OOR) state for 3 ms, LOR state shall be entered. LOR shall be left when the IR state persists continuously for 3 ms.
The value of the logical lane marker is available after descrambling.
Each of the four lanes shall have recovered a unique logical lane marker value in the range 0 to 3. If all four logical lanes have different values, the bytes of each logical lane shall be written into an elastic store with the indication of the start of the logical lane 16320-byte period boundary in line to the logical lane marker.
If the bytes of the Lane signals can be written consistently into the elastic store under the presence of a differential delay in line to the particular adaptation function without exceeding the buffering time, the in-multilane-alignment (ILA) state shall be entered. In this case the differential delay can be compensated.
If two or more logical lanes have the same logical lane marker value, or if one or more logical lane marker recovery processes are in the LOR state, or if the differential delay between two logical lanes exceeds the maximum delay that can be compensated in accordance to the related sink function, multi-lane alignment is not possible and the out-of-multi-lane-alignment (OLA) state is entered.