EJECUCIÓN DE LA LPA

If you review the laws in Table 2-7 and correlate them to the text in the previous section, you’ll see that I missed the last two (De Morgan’s theorem). These two laws are not typically used during basic logic equation reduction because they typically involve converting part of an equation into an NAND or NOR gate, which is important when finally implementing a logic function in actual electronics. Another important aspect of optimizing for technology is adding functions out of the leftover gates in your circuit; by looking at how differently a logic circuit could be implemented, you may be able to add functionality to your circuit, without adding any cost to it.

So far in the book, I haven’t discussed the ‘‘Exclusive OR’’ (XOR) gate in a lot of detail, but it is vital for implementing binary adders, as I will show you later in the book. In the first chapter, I presented the XOR gate with the truth table shown in Table 2-9.

You should probably be able to create the logic equation for the XOR table as:

Output¼ ð!ABÞ þ ðA!BÞ

which does not seem like a very likely candidate for optimization. Similarly, you probably would have a hard time believing that the following logic equation would perform the same function:

Output¼!ððABÞ þ!ðAþBÞÞ

But, using De Morgan’s theorem as well as the other rules and laws from Table 2-7, I can go through the manipulations shown in Table 2-10 to show that they are equal, as well as count out the gates required by intermedi- ate steps to give you a list of different implementations of the XOR gate. Each intermediate step in Table 2-10 is an implementation of the XOR gate that you could implement using the number of gates listed to the right of the terms.

It’s interesting to note that a total of five gates is required for each implementation – this is not something that you can count on when you are working at optimizing a circuit.

The basic gate used in TTL is the ‘‘NAND’’ gate: this means that the three basic gates (AND, OR and NOT) are built from multiples of it, as I’ve shown in Fig. 2-9. The basic gate for CMOS is the NOR gate, and Fig. 2-10 shows how the three basic gates are implemented for it. The three gate NAND and NOR equivalencies for the OR and AND gates, respectively, are perfect examples of De Morgan’s theorem in operation. These implementations

Table 2-9 XOR gate truth table.

A B A ^ B

0 0 0 0 1 1 1 1 0 1 0 1

can be checked against De Morgan’s theorem and the rules and laws presented in Table 2-7.

By understanding how gates are implemented in chips, we can now look at how to optimize the gates to provide the fastest possible operation of the logic function. Using the example of the XOR gate, we can graphically show how the gate is implemented using ANDs, ORs and NOTs and how these gates are implemented as NAND gates in TTL chips (Fig. 2-11).

Looking at the bottom logic diagram of Fig. 2-11, you can see that there are two sets of NAND gates wired as inverters together. Going back to Table 2-7, we can see that a doubly inverted signal is the same signal, so we can eliminate these two sets of NOT gates, as shown in Fig. 2-12. The resulting XOR circuit will pass signals through three NAND gates, which

Table 2-10 Different implementations of the XOR gate.

Terms NOTs ANDs ORs NANDs NORs

(!AB)þ(A!B) 2 2 1 0 0 !(!(!AB)!(A!B)) 2 0 0 3 0 !((Aþ!B)(!AþB)) 2 0 2 1 0 !((AB)þ(!A!B)) 2 2 0 0 1 !((AB)þ!(AþB)) 0 1 0 0 2

counts as three ‘‘gate delays’’. This is an example of what I call ‘‘technology optimization’’: the logic circuit has been reduced to its bare minimum, taking advantage of the operation of the basic logic gates that make up the technology that it is implemented in.

Before moving on, I want to take one more look at the home alarm circuit that has been discussed throughout this chapter. I made a pretty bold statement at the start of the chapter, saying that it could be reduced to fit into the most basic TTL chip available – let’s see how honest I was being.

The (repeatedly) optimized logic equation for the home alarm system was:

Alarm State¼ ðW1!W2Þ þ ðPW2Þ

Fig. 2-10. Implementing the three basic gates using NOR gates.

which could be first implemented in two AND, one OR and one NOT gate, as shown in Fig. 2-13 and converted to just NAND gates. You may have noted in Fig. 2-13 the remarkable similarity between the home alarm logic diagram and the XOR logic diagram – as I’ve shown in Fig. 2-14, the logic function reduces to just four NAND gates (one less than the XOR gate built out of NAND gates).

The final home alarm logic function requires four two input NAND gates – which is just what the 7400, the most basic TTL chip, provides. Every TTL chip, except for this one and a derivative revision, has more than four

Fig. 2-12. Optimized XOR gate built from NAND gates.

Fig. 2-13. Home alarm logic circuit built using AND, OR and NOT gates and converted to NAND gates.

gates built into them because they provide additional functions requiring multiple NAND gates. I was not exaggerating when I said that the home alarm logic function could be reduced to the most basic TTL chip available. In the next chapter, I will introduce you to the operation of TTL chips that provide the basis for digital electronic logic functions.

Quiz

1. The three parameters that are used to measure the optimization of a digital electronic circuit are:

(a) Cost, speed and complexity

(b) Gate delay, gate count and technology optimization

(c) Gate count, number of gate delays a signal must pass through and technology optimization

(d) Gate count, number of connections a signal must pass through and technology optimization

2. If TTL logic has a gate delay of 8 ns and the signal passing through an XOR gate built from NAND gates has to go through 9 gates and the shortest path is five gate delays, the time required for a signal to pass through the gates is:

(a) 40 ns (b) 8 ns

(c) indeterminate (d) 24 ns

3. When writing out a truth table, the inputs should be listed: (a) Using a ‘‘Gray code’’

(b) Using a ‘‘binary progression’’ (c) In alphabetical order

(d) In order of importance

4. The ‘‘don’t care’’ bit in a truth table is:

(a) Indicated by a ‘‘dc’’ and replaces the common bits in two true sets of inputs

(b) Indicated by an ‘‘x’’ and replaces the common bits in two true sets of inputs

(c) Indicated by a ‘‘dc’’ and replaces the uncommon bits in two true sets of inputs

(d) Indicated by an ‘‘x’’ and replaces the uncommon bits in two true sets of inputs

5. When optimizing a logic function you can expect:

(a) That the number of chips that are required is reduced from the initial design

(b) That the optimized function runs faster than the initial design (c) Cheaper chips can be used than in the initial design

(d) Answers (a) through (c) are all possible and it might not be able to optimize the circuit from the initial sum of products equation 6. Karnaugh maps are:

(a) Tools designed to help you find your way around a digital electronic circuit

(b) A tool that will help you optimize a logic function (c) The most efficient method of optimizing logic fuctions

(d) Hard to understand but must be used in every logic function design

7. The sum of products logic equation

Output¼ ðA!BCÞ þ ð!A!BCÞ

can be reduced to: (a) A C

(b) !A !B (c) C !B (d) C

8. Which of the following pairs of Boolean arithmetic laws cannot be used together?

(a) Identity and De Morgan’s theorem (b) Associative and idempotent

(c) Complementary and commutative

(d) All the laws and rules can be used together 9. The NAND equivalent to an AND gate is:

(a) Built from two NAND gates and requires two gate delays for a signal to pass through

(b) Built from three NAND gates and requires two gate delays for a signal to pass through

(c) Built from three NAND gates and requires three gate delays for a signal to pass through

(d) Built from one NAND gate as well as a NOT gate and requires two gate delays for a signal to pass through

10. Technology optimization is defined as:

(a) Designing the circuit which uses the fewest number of chips and signals pass through it as fast as possible

(b) Implementing logic functions to take advantage of the base logic of the logic technology used as well as using any leftover gates

(c) Finding the most efficient digital electronic technology to use for the application

(d) Designing circuitry that dissipates the least amount of heat to perform a desired function

CHAPTER

Creating Digital