Process Reaction Times Without Constant Bus Cycle Time and Isochnrone Mode If a drive engineering or other application requires short and reproducible (that is, repeatable, of equal length) process reaction times, then the individual free cycles of sub-components can have a negative effect on the overall reaction time.
In the previous example, the behavior is depicted without constant bus cycle time and cycle synchronization by using a model structure with a DP master, two DP slaves, a programming device (PG) and an OP. This configuration yields the following subcycles, with their own cyclic and acyclic portions:
• Free OB 1 cycle of the user program. A cyclic program branching can cause variations in cycle time length.
• Free, variable DP cycle on the PROFIBUS subnet consisting of:
- Cyclic master-slave data exchange, DP slave 1.
- Cyclic master-slave data exchange, DP slave 2.
- Acyclic portion for interrupts, bus acceptances or diagnostic services.
- Forwarding the token to a programming device (PG), followed by its processing.
- Forwarding the token to an OP, followed by its processing.
• Free cycle on the DP slave backplane bus.
• Free cycle for signal preparation and conversion within the electronic submodules on the DP slave.
Configuring the Distributed I/O (DP)
If especially short and secure process reaction times are desired, then free cycles with different lengths have a definite effect on process reaction times.
With regard of the individual cycling of the input electronic module, signal or data exchange occurs through the DP slave backplane bus, the master-slave data exchange on the PROFIBUS subnet on to the OB 1 user program on the CPU.
The process reaction is determined in the OB 1 user program and is then sent back over the same route to the output electronic submodule. The different lengths and the "random" position of individual cycles have a pronounced effect on process reaction time. Depending on the position of the individual cycles, information transmission can either occur immediately or after two cycles.
Configuring the Distributed I/O (DP)
Process Reaction Times with Constant Bus Cycle Time and Clock Synchronization
SIMATIC produces reproducible (that is, repeatable, of equal length) reaction times by means of a constant (isochrone) DP bus cycle and synchronization of the individual cycles previously listed.
In this case, the situation corresponds to the example given above with the difference that all cycles (up to the OB 1 cycle) are of equal length and
synchronously cycled. The clock pulse generator is comprised of the DP master constant bus cycle time clock that is sent as the global control frame to the DP slaves. A synchronous cycle interrupt OB 61 (or OB 61 to OB 64) ensures that it is synchronized with the user program.
Configuring the Distributed I/O (DP)
With constant bus cycle time and cycle synchronization, all cycles concerned have the same cycle time and length. This keeps the process reaction times of equal length and, because there are no cycle jumps, they are also shorter. This means that the previously described case in which information transmission can occur in the first or second cycle, depending on the position of individual cycles, now no longer applies.
In the previous example, the DP master handles the cyclic master-slave data exchange with slaves 1 and 2. After this comes the processing of the acyclic portions for interrupts, bus acceptances or diagnostic services. The DP master then retains it for a reserve time until the configured constant DP bus cycle time has expired in order to compensate for possible network disturbances and retrieve possible message frame repeats. At this point, a new DP cycle starts with the global frame (GC).
To ensure that consistent status information for the DP inputs can be read at the start time of a new DP cycle, the read process must be moved up by the specified time Ti. This time Ti includes the time for signal preparation and conversion at the electronic submodules and the time for processing at the inputs on the DP slave backplane bus.
Configuring the Distributed I/O (DP)
The period starting at the point when an input is detected at the electronic module to the reaction at an output results in a constant processing time of Ti + TDP + To. This condition ensures a constant process reaction time described by: TDP + Ti + TDP + To.
Prerequisites and General Conditions
• H-systems (redundant/fault-tolerant) do not support cycle synchronization.
• In F-systems, cycle synchronization cannot be used for non-failsafe I/O devices/peripherals.
• Cycle synchronization cannot be used on optical PROFIBUS networks.
• Constant bus cycle time and cycle synchronization are only possible with the
"DP" and "User-defined" bus profiles. However, using the "User-defined" profile is not recommended.
• Cycle synchronization is only possible with DP interfaces integrated in the CPU.
• At a cycle-synchronized PROFIBUS-DP, only the constant-bus-cycle-time master can be the active station. OPs and programming devices(PG) (or PCs with PG functionality) influence the timing of the constant-bus-cycle-time DP-cycle. For this reason, they are not recommended.
• Cycle synchronization among chains is not possible at this time.
• Cycle-synchronized I/O devices can only be processed in process image partitions (part process images). Process image partitions are required to achieve consistent, cycle-synchronized data transmission. Without them, consistent, cycle-synchronized data transmission is not possible. To ensure that a process image partition remains consistent, STEP 7 monitors the quantity of data (the number of slaves and number of bytes per process image partition for the DP master system are limited). In addition, please observe the following points:
- Within a station, input addresses must not be assigned to different process image partitions.
- Within a station, output addresses must not be assigned to different process image partitions.
- A common process image partition can be used for both input and output addresses.
• In HW Config, the address of the cycle-synchronized analog I/O devices must be located in the address area of the process image partition.
• Cycle synchronization is only possible with ET 200M and ET 200S devices;
synchronization with centralized I/O devices is not possible.
• Full cycle synchronization "from terminal to terminal" is only possible if all components in the chain support the "Isochrone mode" system property. When selecting devices in a catalog or in the hardware catalog, make sure that the information field for the modules contains the entry "Isochrone mode". The latest updated list is available in the Internet at
http://www.ad.siemens.de/support, Entry ID 14747353.
Configuring the Distributed I/O (DP)