Understanding the switching characteristics of IGBT is essential to estimate its switching loss. Fig. 2.12 shows the detailed switching waveforms of IGBT under inductive load condi- tion. As shown in the figure, the switching process can be divided into ten phases, five for turn-on process and five for turn-off process.
The ten phases for IGBT switching process are listed below: 1. Gate voltage rise to VT H.
2. IC increase.
3. IC recovery due to diode reverse recovery.
4. VGE plateau.
VGE VCE IC 1 2 3 4 5 6 7 8 9 10 Time Time Time IL VDC Vdep VTH VGG(on) VGG(off) Vd IL+IRR
Switch on Switch off
6. VGE fall.
7. VGE plateau.
8. VCE rise.
9. IC fall.
10. IC decay to zero.
The IGBT turn-on process starts from phase 1, when a positive gate drive voltageVGG(on)
is applied between the gate and emitter. VGE starts to rise towardsVT H and chargesCGE and CGC. Therefore, the time constant of theVGE rise curve can be given byτ1 =Rg(CGE+CGC). CGE is small when IGBT is off as discussed in previous section, hence the rise of VGE is
dominate by CGC. IGBT is off until VGE increase above VT H at the beginning of phase 2.
In phase 2, VGE continues to rise as in phase 1. The inversion layer is built by VGE and
starts to conduct current, henceIC begins to rise. As electrons inject from the emitter to the
drift region from the MOS channel, holes starts to inject from the p-type collector into the drift region to neutralise the space charge. The excess carrier density starts to rise hence the depletion layer shrinks and lead to the drop of VCE. VCE in this phase is controlled by the
combination of voltage drop across depletion layer (Vdep) and the drift region voltage drop
(Vd). Vdep decreases exponentially as the depletion layer retreats while Vd increases as IC
rises. Since load current (IL) is almost constant, IC rises to its maximum value (IL+IRR) at
the end of phase 2 due to the diode reverse recovery current. The MOS channel in this phase is saturated since VCE is still high. Therefore, the MOS current (IM OS) can be calculated
by Eqn. 2.59. Here, KP L is the MOS transconductance coefficient. IM OS =
KP L
2 (VGE −VT H)
2 (2.59)
In phase 3, IC drops from its maximum value towards its steady state value IL as the
shrinks towards the P-well. Vd starts to drop from its maximum value with the decrease of IC. The drop of these two voltages leads to the further decrease of VCE. As VCE decreases,
the depletion layer under gate shrinks laterally from the MOS channel towards the center of interchip region. The positive gate charge started to attract free electrons under the gate and forms the accumulation layer, which lead to a significant increase of CGC.
During phase 4, VCE continues to drop because of the depletion layer shrink and the Vd
drop due to increasing free carrier density in the drift region. However, the voltage across the MOS channel is still high enough to maintain its operation in the saturation region. VGE
is therefore clamped to the plateau value to main the constantIC. Most of the positive gate
current (Ig) flows into CGC to help build up the accumulation layer. Ig can be calculated
from Eqn. 2.60, with VGE,IM OS indicates the required VGE to support the MOS current.
According to the equivalent circuit shown in Fig. 2.11, this could cause VCE to decrease at
a rate shown in Eqn. 2.61.
Ig = VGG(on)−VGE,IM OS Rg (2.60) dVCE dt = dVGC dt = Ig CGC (2.61) Once VCE decreases significantly and close to its on-state value, the MOS channel enters
the linear operation zone. VGE become unclamped and starts to rise towards VGG(on) at
a time constant of τ2 = Rg(CGE + CGC). Note that τ2 > τ1 since CGC increases as the
accumulation layer forms. The increase of VGE will lead to the further reduction of MOS
channel voltage hence VCE drops slightly with the rise of VGE and finally reach it steady
on-state value.
The IGBT turn-off process is almost the inverse sequence of the turn-on process and consists of the last 5 phases. At the beginning of phase 6, the positive gate drive voltage (VGG(on)) suddenly change to a negative value VGG(of f). This causes the discharge of CGE
and a negative gate current through Rg. MOS channel operates in the linear region during
on-state, hence the MOS channel voltage increases with the drop ofVGE, which leads to the
slight rise ofVCE and a constant IC. The voltage drop ofVGE due to the discharging of gate
capacitance follows the time constant τ2.
At the start of phase 7, VCE is high enough to force the MOS channel to enter the
saturation region. Hence VGE is clamped to a constant value to hold the constant load
current and consequently enters the plateau region. Therefore the negative gate current is contributed by the discharging of Miller capacitance (CGC). As the accumulation layer
disappears from the center of the interchip area towards the MOS channel, CGC starts to
decrease and the resistance of the drift region increases which lead to the rise of VCE and
can be calculated by Eqns. 2.60 and 2.61.
The process enters phase 8 whenCGC is reduced significantly and its discharging current
cannot support the negative gate current. CGE starts to discharge hence lead to the decrease
of VGE and consequently IC. Less excess carriers are injected into the drift region and the
depletion layer, or VCE, builds up quickly.
At the beginning of phase 9 asVGE falls below VT H, the MOS channel vanishes hence all
the DC voltage are now applied over the IGBT. As the MOS channel disappears, IC drops
sharply and produces a voltage across the circuit stray inductance (LS) in the same direction
asVDC. This leads to theVCE turn-off overshoot and therefore forward bias the free-wheeling
diode. The current then commutates from IGBT to diode. The VCE overshoot decays when di/dtdecreases as the current commutation between IGBT and diode completes. Note that, there might be some small oscillation in IC at the end of this phase due to the interaction
between the capacitance of IGBT and the stray inductance. VGE, IC and VCE reaches their