Emmanuel Mounier

This diagram shows the SIMD control, represented by a dashed line, as three concentric loops. These loops represent the three stage pipeline used for SIMD control. The MIMD control, represented by the dotted line, only has two loops, representing the two stage MIMD pipeline. The transitions between the two pipeline schemes are represented by the two

lines labelled 'ESCAPE', and 'LOCAL OFF or STOP'. The diagram shows how

these lines are used to jump between the two pipeline schemes. The 'LOCAL OFF or STOP' transition results in a change from the two stage pipeline to the three stage pipeline, while the 'ESCAPE' transition changes from the three stage to the two stage pipeline.

Both transitions require special control to synchronise, and to adjust between the different pipelining schemes. The problems found in implementing these transitions are discussed below, and the solutions finally used are presented.

6.5.1 Transition from MIMD to SIMD

This transition is performed by either the LOCAL_OFF or STOP

instructions. These two instructions require synchronisation to occur

before SIMD control can commence. The different requirements for these two instructions are as below:

•LOCAL OFF

This instruction is used to switch to SIMD control to execute the next virtual neuron. To synchronise this transition relies upon waiting for the synchronisation signal that is sent with the first instruction in the SIMD nroeram. NOP instructions are inserted until this synchronisation sienal arrives.

•STOP

This instruction is used to synchronise the start of each network update, and requires the processor to wait until the start signal is generated by the external input and output hardware. NOP instructions are again inserted until this signal is set. Once

Richard Palmer Phd. Thesis

this signal is generated, the processor synchronises with SIMD control using the technique given above.

6.5.2 Transition from SIMD to MIMD

The transition between SIMD and MIMD control presents a problem that is

very similar to the execution of conditional branch instructions in

conventional processors. Such conditional branch instructions present

problems when they are performed on a pipelined architecture^]. This

problem is highlighted below, and possible solutions to this are presented.

The problem that occurs in conditional operations on a pipeline is that the condition only becomes valid after the instruction that sets the condition has been executed. This results in the condition being set too late for the next instruction to use. This problem is outlined below:

FETCH instr n FETCH instr n+1 FETCH instr n+2

EXEC instr n-1 EXEC instr n* EXEC instr n+1

* Condition for instr n valid here.

In this case instr n+1 cannot use the conditions set by instr n. The first instruction that can use these conditions is instr n+2.

Unless special attention is made, the instruction following the branch instruction (instr n+1) may be incorrectly executed. To ensure this does not occur one of several techniques can be used:

•Page-Mode Access

Processors that use on-chip microcode can make use of a technique called page-mode access. An example of such a processor is the Motorola 68000.

The operation of this mode relies upon organising the microcode so that all possible conditional outcomes are held in the same row in memory. This then allows the condition to be evaluated as normal, and the row to be selected at the start of the next clock

Richard Palmer Phd. Thesis

phase. This scheme eliminates any latency in the conditional branching.

In the example below the row select for instr n+1 is made before the condition is established. Once the condition is established the column select and execution occurs together in the same clock cycle.

ROW SEL instr n ROW SEL instr n+1 ROW SEL instr n+2

COL SEL instr n-1 EXEC instr n-1

COL SEL instr EXEC instr n*

n COL SEL instr n+1

EXEC instr n+1

Condition for instr n valid here.

•Insert a NOP

By inserting a NOP after the conditional instruction, an extra cycle is made available during which the conditions can be correctly evaluated. This allows the conditional branch to occur without the accidental execution of the instruction following the conditional branch.

In the example below a NOP instruction is executed before instr n+1. This NOP ensures that all conditions are valid before instr n+1 is executed, thus enabling a conditional branch to occur correctly.

FETCH instr n FETCH nop FETCH instr n+1

EXEC instr n-1 EXEC instr n* EXEC nop

Condition for instr n valid here.

The use of NOP instructions in this manner can be likened to introducing 'bubbles' into the pipeline scheme. These 'bubbles' can seriously impair the performance of a pipelined processor, and

many techniques have been proposed to remove them. These

techniques rely upon complex compiler algorithms to resolve any dependencies, hence minimising the cost of conditional branches.

Richard Palmer Phd. Thesis

To achieve this re-ordering of instructions is performed. Compilers for many RISC processors move instructions from either before an conditional branch, or from one of the target of the conditional branch, to the instruction just after the branch (instr n+1). The MIPS R3000 does this using a technique called

delayed branches, while both the SUN SPAB4 and MIPS R4000 use a

technique called annulling branches.

•Delayed Branch

By moving an instruction from before a branch to just after it results in a delayed branch. This instruction is always executed, with the branch occurring on its completion.

In this example the instruction at instr n+1 has been moved from before the conditional branch to just after it. This instruction will always be executed, allowing time for the conditions for instr n to be evaluated. In this example instr n+2 represents the first instruction from the target of the branch.

FETCH instr n FETCH instr n+1 FETCH instr n+2

EXEC instr n-1 EXEC instr n* EXEC instr n+1

Condition for instr n valid here.

•Annulling Branches

By shifting an instruction from one of the branch targets to just after the branch instruction, and conditionally executing it, results in an annulling branch.

In the example below instr n+1 is moved from one of the branch

targets, and will only be executed if that target proves to be

correct. If the branch target is incorrect the instruction is 'annulled' and a NOP is performed.

Richard Palmer Phd. Thesis

FETCH instr n FETCH instr n+1 FETCH instr n+2

EXEC instr n-1 EXEC instr n* EXEC instr n+1

or NOP

Condition for instr n valid here.

•Branch Linking

To improve on the likelihood of this instruction being executed correctly the SUN SPARC, processor and the MIPS R4000 uses two specialised instructions:

These two conditional branch instructions state which of the two branch targets is most common, thus allowing the first instruction from the most frequent branch target to be selected.

•Selected Solution

From these options the annulling branch technique was chosen. This was primarily because there is no convenient instruction that can be moved from before the branch to just after it - so a delayed branch was not possible - and because there is a low probability of the branch being taken.

This solution results in a zero overhead for the branch if control remains under SIMD mode, while a single cycle delay is imposed when a switch is made to MIMD control.

6.5.3 Implementation of Control Switching

The hardware that is used to control the execution of each control type, and to perform the switching between them, is implemented by a finite state machine. This finite state machine controls the instruction multiplexer and the instruction decoder, and provides all the signal required to synchronise and switch between the two different control

Conditional Branch and Link Likely Conditional Branch and Link Unlikely

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