Encuesta sobre las ideas previas de los estudiantes

The base chip (see Figure 2.2.1) is fabricated on a 800 µm thick AlN sub- strate, a non-toxic ceramic which has a relatively high thermal conductivity

of 180 WK−1_m−1 _{[6]. The AlN ceramic is mechanically more stable than}

Si, and therefore provides stability to the chip package. Its relatively rough surface inhibits using it for the magnetic trapping structures on the science chip. The substrate contains 40 laser drilled holes with radii of 300 µm each,13 _{which are used for DC electrical contacting the base chip from the} back. The laser drilling produces Al droplets, which are distributed all over the substrate. Before further processing, these droplets had to be removed by a combination of cleaning with a fiberglass brush, ultrasonic acetone baths and piranha etch.14 _{After cleaning of the substrate, the chip structure is fab-} ricated by electroplating (see schematic on Figure 2.2.2). First, we deposit in a UHV e-beam evaporation chamber a 3 nm Ti adhesion layer, followed by a 50 nm gold seed layer. Then a 8 µm thick layer of photoresist (ma-P 1240 from micro resist technology) is spun on. This photoresist layer is then photolithographically structured using a foil mask.15 _{The exposed gold seed} layer is subsequently electroplated to a thickness of 12 µm.16 _{The “overplat-} ing” of 12µmgold in 8 µmdeep trenches is uncritical for the relatively wide wire structures on the base chip. Subsequently, the photoresist structure is removed using acetone and piranha etch. Then, the unplated seed-layer (in- cluding the Ti adhesion layer) is removed by dipping the chip for 1 minute into aqua regia.17 _{In this step, also the electroplated gold structures are} thinned by∼100 nm.

We glue the spacer chip on the base chip, using the heat conductive glue H77S from Epo-Tek, which is carefully outgassed under vacuum conditions before application in order to prevent any virtual leaks. Furthermore, we take care to apply only a thin layer in order to get good thermal contact between the base and the spacer chip, such that dissipated heat is transported efficiently to the water cooled base chip to avoid thermal damage of the chip. The spacer chip is a high-resistivity Si substrate18 _{like the one for the} science chip. The spacer chip touches some bond wires as well as wires and feed lines on the base chip. Since we want to avoid any cross-talk between the wires in order to be able to define the currents on the 10−5 _{level, the}

13_{The holes in the AlN substrate have been laser drilled by A.L.L. Lasertechnik GmbH,}

München

14_{Piranha etch is a highly reactive mix of sulfuric acid and hydrogen peroxide. We use}

a mixture of 96% H2SO4 and 33% H2O2 in the volume ratio of 4:1. CAUTION!Never increase H2O2 concentration beyond 3:1 and never bring piranha etch in contact with organic solvents; this would result in an explosion.

15_{From Zitzmann GmbH, Eching. The masks have a resolution of 16’000 DPI.} 16_{Using an ammoniumsulfite-gold solution from Metakem.}

17_{Aqua regia is a mixture of water, hydrochloric acid and nitric acid with volume ratios}

H2O : 32% HCL : 65% HNO3= 1 : 3 : 1. It dissolves Au as well as Ti.

a) evaporate gold seed layer b) spin on photoresist c) UV exposure d) develop photoresist e) electroplate gold U + − ammoniumsulfite- gold-solution Au+ Ti /Pt an o de f ) remove photoresist g) gold etch to remove seed layer

Figure 2.2.2: Schematic illustration of the fabrication process for the elec-

troplated structures. Electroplating allows time and material efficient pro- duction of relatively thick structures. The process steps are explained in the main text. The Figure has been taken from [69].

spacer has to be highly isolating. Neither does the 2 nm native SiO2 layer

provide enough isolation, nor does the bulk resistivity of the high-resistivity Si, where ρ _∼ 104_{Ωcm. Therefore, we oxidize a 20 nm layer of SiO}

2 by

thermal oxidation at 1100 °C. The substrates oxidized in this way exhibit a measured DC resistivity > 40 MΩ. Since the thermal conductivity of SiO2

(1.5 WK−1_m−1_{) is much lower than that ofSi(150 WK}−1_m−1_{), the insulating}

layer should not be grown any thicker than necessary [11].

In the next step, socket adapters with a pitch of 2.54 mm are trimmed and their pins are insert into the laser drilled holes, from the back of the chip (see the right part of Figure 2.2.1). The plugs are mechanically fixed using the glue Epo-Tek 353ND. For electrical contacting of the SMD capacitors, mini-SMP jacks19 _{as well as the DC pins, we use the indium solder reflow} paste Indalloy 204.20 Indalloy 204 has a melting point of 170°C and consists of 70% In and 30% Pb. After the solder paste is applied, we put the chip on an aluminum block21 _{with temperature monitoring, and heat the block on} a hotplate at a ramp speed of 10°C per minute to a temperature of 200°C,

19_{from Rosenberger GmbH} 20_{from “Indium Corporation”.}

21_{The glued plugs prevent good thermal contact between the chip and the hotplate if}

hold the temperature steady for about 30 s, until we slowly ramp down the temperature again (-10°C per minute).

Before using Indalloy solder pastes, we tried to solder with conventional Sn based reflow pastes or conducting epoxies like H20F from Epo-Tek. It turned out that soldering gold conductors with Sn pastes does not work because the paste completely dissolves the gold stripe [116], establishing no electrical contact. Furthermore, there seem to be issues with Sn based solder getting brittle when dissolving gold. Using conductive, silver-filled epoxy glues like H20F from Epo-Tek works on a short time scale, but it turned out that electrical contact worsens with time (on the order of weeks) by at least a factor of 10. It turns out to be a well-known problem, which is attributed to an incompatibility of silver-filled glues with Sn, which is contained in the DC pins as well as in the SMD solder pads.22