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The ampliers in each pipeline stage need proper biasing. The biasing current is chosen according to the bandwidth requirement of the amplier, which

is, in turn, dictated by the sampling frequency of the whole converter. It follows that a signicant amount of power would be wasted, when the ADC is operated at frequencies lower than the maximum nominal sampling frequency of 40MHz. Therefore, a biasing strategy has been chosen, which adapts the current through the ampliers to the sampling frequency; gure 4.9 shows this biasing architecture, inspired by the β-multiplier presented in [LB].

VcgP T1 T2 Rint Rext Pad T3 T4 VcgN VDD_ADC_an IR IR

Figure 4.9: Scheme of the ADC biasing core, based on a β-multiplier [LB]. The start-up circuitry is not shown.

Transistors T3 and T4 are a PMOS current mirror; therefore, the same

current IR ows through the two branches of the circuit. Transistor T2 has

a W/L ratio K times that of T1; the biasing resistance R is the sum of Rint

and Rext.

Some circuit considerations give the following equation for the current through the biasing resistor [Ba, 20]:

IR= 2 R2_KP n· W_L11  1 −√1 K 2

where W1 and L1 are the sizes of T1, and KPnis dened in equation 2.2. This

equation suggests that this architecture oers a good PSRR, while allowing an external control on the bias current.

As the scheme shows, the loop of the four transistors creates a positive feedback. This is stable under the condition that the loop gain be less than 1. The loop gain is given by the following expression [LB]:

gm2· gm3

gm1· gm4

· 1

1 + R · gm2 (4.11)

Practically, VcgP will be greater than VcgN, and gm2·gm3will be slightly bigger

than gm1· gm4. Therefore, with a small R, the loop gain would be even larger

than 1. It is clear that R · gm2 is the critical factor which determines the

stability of the loop. With the present design values, the resistance R must be at least 350Ω, in order to have a stable loop with gain less than 1. A potential issue is the presence at the pad level of a parasitic capacitance, which may short high-frequency signal components to ground, decreasing the resistance at those frequencies, thus making the loop unstable [Ba, 20]. For this reason, the resistor R has been split in two components, Rint on-chip,

and Rext o-chip. The on-chip resistance has the safe value of 2.8KΩ; even if

the external resistance is shorted to ground, this internal resistance is large enough to keep the loop stable.

The external resistance Rext can assume values in the range 2-10KΩ.

The nominal value of 3KΩ provides the appropriate current for a sampling frequency of 40MHz; in this case, the reference current IR is 33µA, and the

total analog power consumption of the ADC is 32mW.

The reference voltage VcgP is used to generate several biasing voltages for

NMOS transistors as well as for PMOS transistors; some current mirrors, whose transistors are scaled versions of the transistors in the stage ampliers of the ADC, generate all the needed biasing voltages. In this way, the refer- ence current IR is mirrored as bias current of all the analog components of

the converter.

By changing the value of the external resistor Rext, the user can tune the

current and, as a consequence, the power consumption of the whole ADC, according to the sampling rate needed. Figure 4.10 helps nding the value of Rext for a given power consumption; this dependency reects the 1/R2

law of equation 4.11. Having a bias resistor o-chip can be also useful in power pulsing applications; using a switch to disconnect an external resistor, the reference current IR can be signicantly reduced, driving the ADC in a

low-power state.

In the β-multiplier, the two voltages VcgN and VcgP in gure 4.9 could

remain at ground and supply voltage, respectively; this state would be stable, without any current owing through the two branches [Ba, 20]. In order to avoid this condition, some startup circuitry is added, which creates a low- resistance path between VcgN and VcgP, when these two voltages are too

Figure 4.10: Simulation of the analog power consumption of one ADC as a function of the value of the o-chip biasing resistor.

dierent from each other; this is actually the case also when the o-chip bias resistor is disconnected (shutdown mode). Therefore, the simulated power consumption in shutdown mode of 1.24mW per ADC is due not only to leakage, but also to the startup circuitry for the beta multiplier.

The Super-Altro Demonstrator includes 16 ADCs. Having 16 indepen- dent biasing blocks, each one with an external resistor, would be highly impractical. Therefore, one single β-multiplier is used to provide biasing to all 16 channels; the reference VcgP is routed to each individual channel, where

it is used to mirror IR into the stage ampliers.

This poses the problem of the IR drop with one single β-multiplier. In fact, VcgP is provided to 80 PMOS gates (ve per channel); these gates may

be leaky, and sink some current; since the VcgP line travels all along the chip

to reach all the 16 channels, its resistance is not negligible, and there could be a signicant voltage drop, leading to a biasing current mismatch between ADC channels.

In the present design, the VcgP line is 7.5mm long, and presents a resistance

of 32Ω between adjacent channels, which adds up to 480Ω between the β- multiplier and the furthest current mirrors. The IR drop has been simulated, together with this value of parasitic resistance, and the results show that it does not introduce signicant mismatch between ADC channels.