EQUILIBRADO DE CELDAS

A possible solution to this problem can be spotted easily from Fig. 5.16. We could simply arrange to connect some of the unused head pipes at the INT 13h BIOS interface to some of the unused cylinder pipes at the IDE/ATA disk drive interface. In other words, we could try trading some of the spare head bits (4) at the INT 13h BIOS interface for some of the spare cylinder bits (6) at the IDE/ATA disk drive interface. Clearly, there are many ways in which this trade could be carried out.

One approach that was adopted by the PC industry is to take the maximum number of cylinders value at the IDE/ATA interface and, if it is greater than 1024, determine thesmallestpower of two which when divided into it makes it less than or equal to 1024. We can then think of a cylinder’s address at the IDE/ATA interface as being divided by this power of two before it is passed to the cylinders register at the INT 13h BIOS interface, and, at the same time, a heads address at the IDE/ATA interface as being multiplied by the same power of two before it is passed to the heads register at the INT 13h BIOS interface. Thesmallestpower of two is used because this ensures that the address space at the IDE/ATA interface that is lost by the division and rounding down process is kept to a minimum. Clearly, when moving from the INT 13h BIOS interface to the IDE/ATA interface we can think of a complementary process being carried out whereby a cylinder’s address is multiplied by that same power of two and a head’s address is divided by that same power of two.

This results in the same CHS address having different values at the two interfaces. In order to distinguish between a CHS address at the INT 13h BIOS interface from one at the IDE/ATA interface, we use the terms Logical-CHS (or L-CHS) for CHS addresses at the INT 13h BIOS interface and Physical-CHS (or P-CHS) for CHS addresses at the IDE/ATA interface.

In the preceding discussion, we used the phrase “we can think of ” quite deliber- ately. The elegant idea of simply dividing and multiplying the cylinder and head components of CHS addresses by the same power of two will not work in practice because CHS addresses are whole numbers, and rounding effects of the division will not map addresses uniquely on translation. Consider, for example, a multiplying factor of 2 and the two logical CHS addresses listed below. They both translate, using the simple algorithm of doubling the cylinder number and halving the head number, to the same physical CHS address, as, of course, do many, many more.

L-CHS (4, 6, 10)ÆP-CHS (4 × 2, 6/2, 10) = P-CHS (8, 3, 10) L-CHS (4, 7, 10)ÆP-CHS (4 × 2, 7/2, 10) = P-CHS (8, 3, 10)

A slightly more complex algorithm, based on the same idea, needs to be used in order to achieve both a unique mapping of CHS addresses and a sector ordering on the disk which is consistent46 _{with logical block addressing (LBA), an alternative} addressing system which we describe in a later section. This algorithm may be imple- mented by the following rules, for translating from L-CHS to P-CHS:

46 This is a requirement of the ATA specifications. We show at Appendix 10 the relationship between the two systems.

P-C = (L-C ×N) + (L-H/P-Hn) P-H = (L-H mod P-Hn) P-S = L-S

In these rules, P-C, P-H and P-S are the components of the CHS address at the IDE/ ATA or physical interface; L-C, L-H and L-S are the components of the CHS address at the INT 13h or logical interface; N is the power of two factor; P-Hn is the maximum number of heads at the physical interface; mod is the modulus function and / is the integer division function with the result rounded down. If we now consider the two translations in our example above, assumingNis 2 and P-Hn is 16, we obtain the following:

L-CHS (4,6, 10)ÆP-CHS ((4 × 2) + (6/16)),(6 mod 16),10) = P-CHS (8,6, 10) L-CHS (4,7, 10)ÆP-CHS ((4 × 2) + (7/16)),(7 mod 16),10) = P-CHS (8,7, 10) We now see that the mapping is unique, at least for these values. Further analysis would show that it genuinely is unique and consistent throughout. Because the factor N is always a power of two, these rules may be implemented by shifting bits the appropriate number of places left or right. For this reason it is often referred to as the bit shifting method.

At Fig. 5.17 we have shown the CHS values for a 540 Mbyte hard drive which, at the IDE/ATA (P-CHS) interface, requires a maximum number of cylinders of 1057 (addresses 0 to 1056), a maximum number of heads of 16 (addresses 0 to 15) and a maximum number of sectors of 63 (addresses 1 to 63). We note that, at 540 Mbyte, this drive breaches the 528 Mbyte barrier. Using the approach described above, the maximum number of cylinders value at the INT 13h BIOS (L-CHS) interface is calcu- lated, rounding down, as 1057/2 = 528 (cylinder addresses 0 to 527) and the maximum number of heads value at the INT 13h BIOS (L-CHS) interface is calcu- lated as 16 × 2 = 32 (heads addresses 0 to 31). The maximum number of sectors remains as 63 (sector addresses 1 to 63). The largest L-CHS address (527, 31, 63) is now well within the range of the INT 13h BIOS registers and the disk appears to the

(0 to 1056 in 16 bits) 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 (0 to 15 in 4 bits) (1 to 63 in 8 bits) Cylinders = 528 (0 to 527 in 10 bits) Heads = 32 (0 to 31 in 8 bits) Sectors = 63 (1 to 63 in 6 bits) Cylinders = 1057 Heads = 16 Sectors = 63

IDE/ATA INT 13h BIOS Pipes Pipes Translation algorithms Fig. 5.17 CHS translation.

BIOS, and, of course, to all the software that uses it, to be of a quite different but entirely acceptable geometry.

It should be noted that we can lose some capacity by this translation process. The original disk geometry (P-CHS) of a maximum number of cylinders of 1057, of a maximum number of heads of 16 and of a maximum number of sectors of 63 results in a total capacity of 1057 × 16 × 63 × 512 = 545,513,472 bytes. Using a similar calcu- lation, the INT 13h BIOS translated geometry (L-CHS) results in a total capacity of 528 × 32 × 63 × 512 = 544,997,376 bytes. This is a loss of 516,096 bytes, or about 0.1%. We also note that the largest logical CHS address translates, using the rules described above, to the following physical CHS address:

L-CHS (527, 31, 63) ÆP-CHS ((527 × 2) + (31/16)), (31 mod 16), 63)

ÆP-CHS (1055, 15, 63)

This shows that we have lost a cylinder through translation, the largest available P-CHS cylinder number being 1056. This is a loss of 16 heads × 63 sectors per track = 1008 sectors = 1008 × 512 = 516,096 bytes, the figure that we have already obtained above. We are now in a good position to interpret much of the data that was given by the Find-ATA program for the ST32140A hard disk (see Fig. 5.8). In the “Hardware” column we see that the maximum number of cylinders is 4095, the maximum number of heads is 16 and the maximum number of sectors is 63. The physical disk capacity is shown as 2,113,413,120 bytes. These figures are clearly the P-CHS values for the IDE/ATA interface and we can confirm that 4095 × 16 × 63 × 512 is indeed 2,113,413,120 bytes. In the “DOS” column we are seeing the L-CHS translated values at the INT 13h BIOS interface. The maximum number of cylinders value is calculated as 4095/4 = 1023 (rounding down) and the maximum number of heads value is calculated as 16 × 4 = 64, both as shown in the figure. The logical capacity can then be calculated as 1023 × 64 × 63 × 512 = 2,111,864,832 also as shown in the figure. We also note that the largest logical CHS address translates, using the rules described above, to the following physical CHS address:

L-CHS (1022, 63, 63)ÆP-CHS ((1022 × 4) + (63/16)), (63 mod 16), 63)

ÆP-CHS (4091, 15, 63)

This shows that we have lost three cylinders through translation, the largest P-CHS cylinder number being 4094. This is a loss of 3 cylinders × 16 heads × 63 sectors per track = 3024 sectors = 3024 × 512 = 1,548,288 bytes, which accounts exactly for the difference between the physical capacity shown for the disk of 2,113,413,120 bytes and the logical capacity shown for the disk of 2,111,864,832 bytes.

Considering the other parameters given in Fig. 5.8, we should now be familiar with the terms DMA (Direct Memory Access) and PIO (Programmed Input Output) which we have discussed earlier. The final term, LBA, for Logical Block Addressing, we will consider very shortly.