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The small current output of a TES would be difficult to read out if not for SQUID current ampli- fiers. The designed output impedance of the Bicep2 TESs during operation is 30 mΩ. This low

resistance would be mismatched to the noise of available FET amplifiers. SQUIDs, however, are easily impedance-matched to TESs. In addition, they offer a natural means to multiplex a large number of detectors with fewer wires. If each of Bicep2’s 528 readout channels had a separate pair

of wires running to 4 K the loading of the focal plane would overwhelm the UC fridge stage. The multiplexer reduces the wiring count to the focal plane from 528 to 97 pairs of wires.

2.5.1.1 SQUID amplifier

Before discussing the operation of a SQUID multiplexer, first consider how a SQUID amplifier can be used to read out a single TES, as illustrated in figure 2.1. The current output of a TES is inductively coupled to a single SQUID by an input coil. A feedback coil is also inductively coupled to the SQUID. The amplifier is operated in flux-lock loop (FLL) to linearize the periodic output and increase the dynamic range of the SQUID’s response to input flux. A lock point is selected on a linear, high-gain portion of the SQUID’s V−Φ response curve. As the flux from the input

samples the difference between the output of the SQUID amplifier and the output expected from the lock point. The difference, or error, signal is fed to a digital-to-analog (DAC) converter with a series feedback resistance (Rf b1) that produces a compensating current and flux in the feedback

coil.

The first-stage SQUIDs dominate the noise of the amplifier, so have been designed to provide low noise and high gain. Their low output impedance must be matched to an intermediate, higher-output impedance stage. The 100 SQUIDs of the SSA each have∼1 Ω dynamic resistance for a∼100 Ω

total output impedance that is well matched to room temperature electronics. The first-stage could be coupled directly to the SSA, but the NIST SQUID amplifier uses an intermediate (SQ2) stage for several reasons. The SSA cannot be placed on the focal plane because its high dissipation is too great of a load for the UC stage, so it is placed at 4 K. The first-stage SQUIDs could be connected directly to the SSA, but this would require routing the summing coil to 4 K. The superconducting loop would need to be carefully shielded, since it would generate screening currents for any changes in flux through the large loop area, which would couple flux to the SSA input. Also, the parasitic inductance from the cabling would reduce the coupling efficiency of the summing coil [51][16]. 2.5.1.2 SQUID multiplexer

When a SQUID is biased below Imin

c it will not generate output in response to changes in input

flux. This allows a number of front-end SQUIDs, each coupled to a TES, to share a common readout amplifier. The TESs are continuously biased but are only sampled when the SQUID they are coupled to is biased normal. The off-state SQUIDs are superconducting and contribute no noise, heating or power to the common amplifier chain. In a time-domain multiplexer the SQUIDs are biased on, the output is sampled and then the bias is turned off, in sequence. When all rows in the multiplexer have been visited — a full frame — the multiplexer returns to the first row in the sequence. Due to the finite open-loop bandwidth of the multiplexer each row must be visited long enough for the

amplifier to settle before it is sampled.

In the NIST three-stage SQUID multiplexer 33 first-stage SQUIDs (SQ1s) are coupled to a common amplifier consisting of two additional stages: a second-stage SQUID (SQ2) and a SQUID series array (SSA). There are 16 SQ2s and SSAs, for a 33× 16 multiplexing architecture. The 33

SQ1s are coupled to a single SQ2 on a MUX chip. The output of the SQ2 is routed to the SSA at 4 K. The 16 SQ1s in a row are wired in series with a room temperature bias resistor (Rsq1). This

common bias turns one row or SQ1 on in each column, and is turned on and off sequentially for the 33 rows.

Each SQ1 is shunted by a 1.5 Ω address resistor and an output inductor (Lint). The address

resistance is comparable to the ∼ 1–3 Ω dynamic resistance of the SQ1s, which means the SQ1s

operate between a voltage and current bias. Changes in the SQ1 input flux cause a modulation in the current through the resistor and output coil. Each output coil is coupled to one of 33 inductors (Lt) connected in series in a superconducting transformer loop called the summing coil. In addition

to the common transformer loop, all of the SQ1s are coupled to inductors (Lf b1) in series on a

common feedback line. The feedback line is biased with a room temperature series resistor (Rf b1) to

provide dynamic flux feedback. Since only one SQ1 in a column operates at a time, the transformer and feedback can be shared.

The transformer loop is coupled to the SQ2 by an inductor (Lin2). The SQ2 is flux biased to

a useful lock point by an additional inductor (Lf b2) that is biased by a room temperature resistor

(Rf b2). The SQ2 is shunted by a bias resistor (Rsq2bias) and its circuit is biased by a room tem-

perature resistor (Rsq2). The 90 mΩ SQ2 bias resistance is much smaller than the∼3 Ω dynamic

resistance of the SQ2, so it is operated in a voltage-biased mode. Input flux from the transformer inductor modulates the output current of the SQ2, which is carried to the SSAs located on a circuit board mounted to the 4 K base plate. The SQ2 bias resistors are also located on this circuit board. The SQ2 output lines are wired in series with 100 input inductors (Lina) each coupled to one

of the 100 SQUIDs in the SSA. Changes in the output current of the SQ2 modulate the input flux to the SSA. The voltage response of each SQUID in the SSA adds in phase and boosts the gain and dynamic range of the final amplifier stage. The SSA is current-biased by a room temperature resistor (Rsqa). Flux modulation from the 100 input inductors generates a voltage response that is

fed to the room temperature electronics through the SSA bias lines. Flux bias to control the SSA lock point is provided by 100 series inductors (Lf ba) connected in series to a room temperature bias

In addition, switching transients at the beginning of each row visit generally increase the amount the output must slew (§4.1.5.2).

In order to ensure the amplifier has adequately settled before sampling, the multiplexer must spend a time (τdwell = xτsettle) on the row, where x is a safety factor. Each row is sampled at

the multiplexer frequencyfmux = τdwell1 . The rate at which every row is sampled, or frame rate, is then dictated by the number of channels multiplexed (Nmux) byff rame= _N 1

muxτdwell. The amplifier bandwidth must be a factor Nmux larger than the readout bandwidth required for each detector.

The noise bandwidth — assuming a one-sided PSD — of the amplifier is famp = _2τfmux_dwell, and the

Nyquist frequency of the detector isfN yq =ff rame₂ .

The SQUID amplifier noise power S2

amp is roughly white, which means that the total aliased

noise power in the detector readout will just be the ratio of the noise bandwidth to the Nyquist frequency of the detector:

Stot2 =famp/fN yq= fmux 2τdwell · 2 ff rame =Nmux (2.5)

This Nmux increase in the amplifier noise is the so-called multiplexer disadvantage inherent in a

time-domain multiplexed readout. In order to compensate for this increase in amplifier noise the mutual inductance of the input coil must be increased so that the current noise referred to the input coil of the TES is not degraded, or SI,amptot2 = SΦ,amptot2 /Min. The required level of coupling is

dictated by the relative amplifier and detector noise levels, but to get the same current noise level of an unmultiplexed amplifier the mutual inductance must be a factor of√Nmux higher.

The bandwidth of each amplifier stage has been designed to be as large as possible while equal to the other stages. If the bandwidth of one stage greatly exceeds another the noise bandwidth will go up but without a corresponding increase in the multiplexing bandwidth, which is set by the slowest time constant. Thus the aliased noise penalty will increase. The input-referred noise level decreases

Figure 2.18: Micrographs of a multiplexer chip and close-up of the first-stage and dummy SQUID.

Left: The MUX chip with the first two stages of the SQUID multiplexer is shown. In this view the

NYQ chip is below the MUX chip and the lower wire bonds connect to the output of the NYQ chip circuit. The SQ1 bias wire bonds are shown at the top of the image, but are generally double-bonded to avoid single point failure in the series SQ1 bias lines. The 1.5 Ω address resistors, gradiometric

summing transformer coil, real and dummy SQ1, SQ2 and gradiometric input coil transformer are shown. Note a discrepancy: in this image the input coils of the SQ1 nearest the SQ2 on the far left is connected. Right: The first-stage SQUID is located on the top and the unbiased dummy SQUID is on the bottom of this micrograph. The four, octagonal windings of the SQUID loop are shown, partially covered by the input and feedback coils. Bias for the SQUIDs and output for the SQ2 enters on the lines from the top. The input coil signal enters from the connected horizontal lines on the lower right and the flux feedback lines are overlapping and enter from the bottom. The Josephson junction used in the real SQUID is the first connection — at the center of the cloverleaf — that the address lines make, which creates an asymmetry in the inductance of the two arms of the SQUID loop.

with stages further from the first stage. So the additional penalty is decreased if, for example, the SSA bandwidth exceeds that of the SQ2.