The DNL performance was limited by the shift of capacitor values during the assembly process. Figure2.48 shows a typical DNL curve over the output code. The capacitive matching is independent of the conversion rate, so that the resulting DNL errors are independent of speed. However, a small amount of spikes at particular codes change with varying conversion rate, so that these errors were called ‘dynamic errors’. These errors always appeared in pairs: a long code followed by a short code [16].
An essential amount of research was required to allocate the error source. At these particular codes (40959/40960, 49151/49152 and 57343/57344) the critical bit decisions occur at bit 2 or bit 3, or in other words always when big capacitors are switching. This first pointed to a settling problem of the reference, but modifications in the reference path did not show any improvement. The root cause is the comparator input stage.
Code 49152 for example has the binary format ‘1100 0000 0000 0000’. The CDAC output and therefore comparator input is shown for the four MSBs in
Spikes caused by assembly shift
Thermal effect causing long-short code combination
Code DNL (LSB) 2 1.5 1 1.5 0 –0.5 –1 0 10000 20000 30000 40000 50000 60000
Fig.2.49. The comparator input stage is overdriven during the MSB decision and settles to 0 V during the MSB-1 decision.
The effect for the comparator input stage is illustrated in Fig.2.50. A current source is driving the currentIbiasthrough the differential input pair. The transistor with the lower gate potential will carry more current and will have a higher voltage drop across the resistor.
During the MSB conversion in Fig. 2.49, the comparator input voltage is strongly negative. Therefore,Ibiasis fully routed through the resistorRp, which as a consequence dissipates a higher power and heats up while the resistorRn, which carries no current, cools down. Due to the temperature coefficient, the resistors change their value. One resistance increases the other decreases.
The next bit decision in Fig.2.49features a 0 V input. The currentIbiasis equally distributed toRpandRn. However, the resistors still have a different temperature and therefore a different resistance. This will cause the output voltage of the comparator input stageVout to be different from 0 V. The heat of an integrated resistor caused by an increased current flow can build up quickly, but unfortunately it disappears slowly as it is well isolated by the silicon oxide. This effect is quantized in the following calculation.
The power, which is dissipated inside a resistor can be calculated to PI ¼ I V ¼ I2 R:
The energy, which is dissipated within the resistor during the clock cycle of the MSB decision, is
EI ¼ PI Tclk ¼ I2 R Tclk: The electric energy is converted into thermal energyEth
0.75V CDAC output REF = 4.000V T1 T2 T3 T4 T5 MSB=1 Sampling MSB-2=0 MSB-1=1 MSB-3=0 time Vcomp 0.50V 0.25V 0 V -0.25V -0.50V -0.75V -1.00V
Eth¼ Cp m ΔT;
whereCpis the specific heat of the material of the resistor,m the mass of the resistor andΔT is the change in temperature. The mass can further be extracted by the width W, the length L and the thickness T together with the specific densityρ. For poly resistors, the specific heat is Cp¼ 0:7 gKJ and the specific density is given by
ρ ¼ 2:328 g
cm3. The above equations can now be solved for the change in
temperature
ΔT ¼ I2 R Δt
Cp W L T ρ: ð2:16Þ
The difference in temperature will now cause a drift of the resistanceRp
ΔRp¼ Rp TC ΔT ð2:17Þ
whereTC is expressing the temperature coefficient. Finally, the erroneous output voltage of the comparator input stage ΔVout is calculated below. This dynamic offset voltageΔVoutcan further be referred to an input offset errorΔVinby dividing ΔVoutby the gain of the differential stageg.
a) Comparator during MSB decision b) Comparator during MSB-1 decision
VDD Ibias I bias 0 V out VSS VDD Ibias I bias/2 VSS R p R n Rn Rp Vin=-1V Vin=0V Vout 0V
ΔVout¼ Ibias 2 ΔRp ð2:18Þ ΔVin¼ ΔVout g ð2:19Þ
Now, an example should prove the relevance of the thermal effect. For low noise, the current could be up toIbias¼ 4 mA. The typical load resistance ranges around 500Ω. Length and width of the resistor might be in the range of 4 μm over 50 μm. The poly thickness of poly resistors is often in the area ofT¼ 0.2 μm. Inserting these values into Eq. (2.16) will result in a change in temperature of
ΔT ¼ I2 R Δt
Cp W L T ρ¼ 6:1 K:
Typical poly resistors have a temperature coefficient around TC¼ 800 ppm/K. Together with Eq. (2.17), the drift of resistance calculates to
ΔR ¼ R TC ΔT ¼ 2:4 Ω
Finally, the output and input related dynamic offsetΔVoutandΔVinassuming a gain ofg¼ 10 result to ΔVout¼ I 2 ΔR ¼ 4:8 mV ΔVin¼ ΔVout g ¼ 0:480 mV
If this comparator is used inside a 16 bit SAR ADC with a 4 V input range, then the LSB size is 61μV, so that the thermal effect causes an error of 7.8 LSB. In a particular case, the above calculation matched the measured DNL error very well. The dynamic effect can be minimized with an adequate design and layout, which are presented in Sect.2.3.2.
Unfortunately, reducing the current through the comparator input stage will also increase the noise density of the comparator. A certain amount of current and therefore some error have to be accepted.
The utilized process provides a variety of resistors. The poly resistor was therefore exchanged with a thin film resistor, which has a temperature coefficient close to zero. Unfortunately, this resistor is very thin. The mass is much lower and the thin film resistor can heat up much more than the poly resistor, so that the resistor drift can get significant again.
Therefore the layout needs adjustments. Both 490Ω load resistors were replaced with 20 load resistors in parallel each with the size of 20 · 490Ω. This adds three advantages. First, the current density is lower 1
20
and the thermal effect is reduced. Second, the area is higher by 202, so that the temperature dissipation is improved.
Finally, the two load resistors can now be fingered, so that a‘cold’ finger is in the middle of two‘hot’ fingers. The thermal distribution after one clock cycle will also warm up the current free resistor, which is illustrated in Fig. 2.51, where the temperature distributionT is drawn over the X-coordinate at the resistor array.
The large resistor area could generate a high capacitance to the substrate. Fortunately, all the oxides between the thin film and substrate are about four times thicker than poly to substrate. Also, the influence of the parasitic capacitor to the bandwidth of the input stage can still be neglected if compared to the parasitic gate capacitance of the second differential input pair. Disadvantageously, addi- tional masks are required for the thin film resistor.
Layout optimizations will only help to some extent. Additionally, a dynamic error correction was introduced, which is not only correcting the dynamic error of the comparator, but also settling effects.