Eventos relacionados con los procesos virtuales en centros de información

There are two phases in reliability engineering, i.e., process development phase and manufacturing phase. In the process development phase, each mechanism that can result in device failure is studied. An interesting and very important aspect of accelerated testing is that not all failure mechanisms accelerate in the same way. For instance, gate oxide breakdown is accelerated by increasing temperature, but hot carrier degradation, on the other hands, needs a lower temperature in order to be accelerated.

Therefore, especially in the phase of process development, each mecha-nism needs to be studied separately. This is typically done on dedicated test structures that are tested on the wafer or are individually packaged. The physics should be understood, and from this the best methods for acceleration and reliability prediction can be determined.

phase, even after 10 years (~1E5 hours) [2]

conditions, as obtained from accelerated tests. Note the absence of the wear-out Extrapolated failure rate at user conditions

versus time (from set tests)

1E+2 1E−2 1E- 1 1E+0

1E+3 1E+4 1E+5 1E+6

time [hours]

failure rate [a.u.]

Reliability environmental stress tests are used to simulate the end use (customer) environment and to uncover specific materials and process related marginalities that may be experienced during operational life.

Historically, a number of standard tests have been defined to accelerate and capture specific device environments. Military standard environmental stress tests and conditions were developed in the 1940s for ceramic package devices being produced for the U.S. Military. Similarly, BellCor (now Telcordia) developed Network Equipment – Building System (NEBS) test standards for the communications use environment in which the use patterns, fault tolerance and seasonal use ambient environments were accounted for in the tests. Other consortiums such as Joint Electronic Device Engineering Council (JEDEC) and Institute for Printed Circuits (IPC) have adapted, documented and standardized many of the same tests. The following lists many of the types of environmental testing along with brief descriptions or reliability issues intended to be uncovered by the test.

2.1 Burn In

Burn in refers to an electrical overstress used in manufacturing and test and eliminate detect infant mortality failures or process defects that may remain latent until early customer operation. Burn in and high voltage extended life tests (HVELT) bake tests are performed on a functional device at high voltage conditions to discover defect failure modes that may failure in early life or extended operation. Early transistor gate defects and breakdown can be detected in burn-in and HVELT tests. Failure data are converted to a defect probability value that can be used to monitor process health.

2.2 Biased Moisture Test

Accelerated biased moisture tests are used to simulate the reliability of a powered device in an elevated temperature and high humidity environment under at nominal run state static bias. The tests are used to find metal migration, corrosion, dielectric breakdown, de-lamination and adhesion issues. Metal migration occurs by two modes, surface and bulk or interfacial diffusion of metal ions driven by an electric field. Corrosion occurs due to the interaction of heat, moisture and stress in a metal. Polymer dielectric breakdown and de-lamination failures are driven by moisture intrusion into the materials where it acts as a plasticizer by hydrolysis or it interferes the mechanisms of interfacial bonding.

There are two standard forms of the biased moisture test that can be employed. The temperature, humidity bias (THB) test is performed at

atmospheric pressure and temperatures between 30°C to 85°C and between relative humidity (RH) 50% to 85%. The highly accelerated stress test (HAST) is performed at less than 3 atmospheres of pressure and at static temperatures between 110°C to 156°C.

2.3 Unbiased HAST and Steam Test

The Unbiased HAST is performed to evaluate non-hermetic packaged devices in humid environments. The test employs temperature and humidity to accelerate the penetration of moisture through the external protective

2.4 Bake and Extended High Temperature Storage Test

Accelerated temperature bake testing is used to simulate a use environment where a device is continuously powered or stored at high temperature. The test is used to uncover solid-state metal reactions and stress voiding (Al) that result in cracks from volume changes, crystallization or trace shorting due to an affinity for an adjoining metal. Intrinsic polymeric materials degradation and creep can also result from the breaking of bonds and/or deformation at high temperatures because of corrosion or oxidation enhancement. Bake testing is performed under a number of different temperatures although some standards are defined. When determining the bake condition it is important to select temperatures that do not result in solid-state reactions that will not occur in use or that will not result in excessive plastic deformation, which may change the failure mode.

material or along the internal build-up or joined interfaces. Bias is not applied in this test to ensure the failure mechanisms potentially overshadowed by bias can be detected (e.g. galvanic corrosion). This test is used to identify failure mechanisms internal to the package and is destructive.

An autoclave test or steam test is similar to the HAST test in that it is per-formed to evaluate non-hermetic packaged devices in humid environments by accelerating moisture penetration. Steam is different from HAST in four respects; fixed temperature (121°C), fixed RH (100%), controlled ramp up/

down and application of bias. Steam test conditions cannot be varied but durations can be altered when not testing to a standard based requirement.

While both steam and HAST/THB remain standards based requirements the only HAST/THB can be used for performance characterization and use condition modelling.

2.5 Electromigration Testing on Devices and Packages

Electromigration in devices results from the “electron wind” effect caused by high current density that is responsible for picking up individual electrons and moving them in the direction of current flow. High current densities (1 x 10⁶ A/cm²) are commonly found in devices interconnects, package bumps and some package vias and traces. Geometry factors such as bent trace can result in current pinning or high local current density in some traces and vias, which then results in reduce reliability over time. The behaviour was first empirically modelled by Black as following an Arrhenius relation with the addition of geometric factors. The data generated form the EM test allows proper design of metal trace and vias relative to the expected use current and temperature. The test can also be used in the

2.6 Moisture Sensitivity Test

Moisture preconditioning is required prior to reliability environmental stresses for all parts that are surface mounted to boards. Preconditioning was introduced as a qualification requirement with the release of plastic package because of “popcorning” during surface mount (see Chapter 6 for more details). The popcorn effect results from expanding steam that is evolved during surface mount. The humidity in the local ambient environment contributes to absorbed moisture over time where maximum absorption scales with temperature. The steps for preconditioning include 5-cycles of temperature cycle (–40 to 60°C), Bake (125°C) and temperature-humidity soak to target the needed moisture level and sit time. Preconditioning tests generally insure that the temperature, humidity and/or the shipping requirements are performed before assessing the use reliability.

2.7 Temperature Cycling and Temperature Shock Tests

Temperature cycle testing is used to simulate both ambient and internal temperature changes that result during device power up, operation and ambient storage in controlled and uncontrolled environments. Temperature cycling tests are used to detect thermal-mechanical interactions that result in dielectric or conductor cracking, fatigue and adhesion issues. Cracking, excessive strain, or fatigue results from differences in the coefficients of thermal expansion the various device materials.

Temperature cycle and temperature shock tests may be distinguished by the rate at which temperature is applied to the either the entire device or a manufacturing environment to monitor process equipment and reprodu-cibility.

local area of the device. Temperature shock (TS) and power cycle (PC) occur at very high temperature ramp rates on the entire device or at local areas, respectively. The TS test can be done in the “air to air” or “liquid to liquid” environment while temperature cycle typically occurs only in air.

The operating specification for temperature cycling is found in JESD-22-A104B. Both tests can be used to detect cracks that result from very fast coefficient of thermal expansion (CTE) changes in the materials which make up the device. Thermal cycle testing is typically performed at slower ramp rates and longer temperature dwell times to allow mechanical damage such as fatigue and creep to occur.

Table 1. Common thermal cycling test conditions

2.8 Power Cycle Testing

The power and temperature cycling test is used to assess the capability of a device to withstand alternate power/temperature exposures extremes at operating biases. This test method applies to devices that are subjected to multiple temperature excursions as required by powering the device on and off. Power cycle tests are not accelerated environmental tests but rather they are accelerated in time relative to use operation. The test is best used at interfaces where the time-dependent interactions between materials near the power source need to be assessed. In many ways the test resembles a thermal shock test between constituent materials in the system where one side of an interface heats rapidly and the second interface material is undergoing nearly instantaneous changes in temperature and mechanical state. The test is not intended to simulate slow changes to temperature and the accumulation of damage but rather to test the instantaneous interactions between materials.

Environmental Test

Low Temperature (°C)

High Temperature (°C)

Soak Timee (minutes)

Cycle Time

TS –65 165

–55 125

TC –65 165 15 30

–55 125 15 30

–40 85 30 60

–40 125 30 60

PC 25 80 2 6

30 80 2 6

30 110 2 6

2.9 Mechanical Testing

Mechanical shock and vibration testing is commonly used to simulate the transportation and use events that are experienced by components on a system board. Shock is a high rate change in velocity and momentum that occurs when devices are dropped or experience high rates of acceleration.

Vibration occurs during all forms of transportation at various vibration and resonant frequencies. The Vibration test is intended to determine the ability of component to withstand moderate to severe vibration as a result of motion produced by transportation or use operation. In addition, design issues with resonant frequency acceleration can be assessed.

The alternative names for the above tests commonly used in semiconductor industry are listed below and summarized in Table 2.

• DHTL: Dynamic High Temperature Life

168 hours (1 week) to test EFR (Early Failure Rate) 1008 hours (6 weeks) to test IFR (Intrinsic Failure Rate) Few hours: usually called burn-in

• SHTL: Static High Temperature Life

• DLTL: Dynamic Low Temperature Life

• HAST: Highly Accelerated Steam Test

• UHAST: Unbiased Highly Accelerated Steam Test

• TMCL: Temperature Cycle

• PPOT: Pressure Pot Test

• U-POT: Unsaturated Pressure Pot Test

• THBS: Temperature Humidity Bias Stress Table 2. Typical reliability tests and their conditions

Temperature Humidity Bias on Typical duration Comment D/SHTL 150°C junction Not applicable Y 48/168/1008

hours

Sensitive for die faults DLTL –40°C ambient Not applicable Y 168/100 hours Seldom used

HAST 132°C 85% Y 96 hours Corrosion

UHAST 132°C 85% N 96 hours

TMCL –65°C/150°C N.A. N 200 or 500 cycles Package – die interaction

PPOT 121°C 100% N 96 hours Trend is

towards unsaturated tests

U-POT 130°C 85% N 96 hours See above

THBS 85°C 85% Y 1008 hours Too slow:

trend is as HAST

2.10 Design for Manufacturability, Reliability, and Testability (DfMRT)

Design for manufacturability, reliability, and testability (Df MRT) is the systematic process of preventing and eliminating designed-in failures in the early stages before actual physical prototyping. Regardless of product application, DfMRT is an important factor in system design, development, qualification, manufacture, and in-service management.

Design for manufacturability (DfM) is a process to make sure that the design is compatible with the manufacturing process, because process incompatibility not only causes quality problems (yield), but also reliability problems. In order to succeed, the manufacturing process must be fully defined and under good statistical control.

Design for reliability (Df R) is the systematic process of preventing or eliminating designed-in failures. DfR includes:

• Perform a proper Failure Modes and Effects Analysis (FMEA) to discover potential failure modes inherent in the design

• Analyse the failure modes and determine their root cause

• Modify the design as such towards optimal robustness

Design for testability (DfT) concentrates on making the design as such that it can be tested easily and/or cost-effectively in later stages.

Design rules and/or guidelines provide tools to perform DfMRT. For example, to prevent wear-out failure, design rules are generated during process development. As long as designers obey all design rules and users obey the maximum use conditions (like maximum temperature and voltage) wear-out is negligible. Design rules and/or guidelines can take the form of theoretical, empirical, or regulatory models that relate potential failure mechanisms and the average life of the product to the life-cycle requirements of manufacturing, assembly, testing, storage, handling, transportation, operation, and repair.

There are also design rules that make an IC less sensitive for process-induced damage. Plasma etching for instance results in a harsh environment for circuits. Long metal lines are exposed to a plasma and may be charged, and may discharge through the gate oxide of a transistor. This will lead to partially degraded transistors, and therefore a reduced reliability. There are design rules for metal layout that minimize these effects, thereby decreasing the amount of stress on IC’s even before they reach a consumer.

In a similar way, there are mechanical stress related rules that prevent too high mechanical stress on the chip in a package. In addition, there are rules to decrease the packaging related yield loss, like die size in relation to die pad to prevent glue short circuit fails.