The maximum allowable clock skew is 2 ns. This specification applies not only at a single threshold point, but at all points on the clock edge that fall in the switching range defined in Table 4-8 and Figure 4-10. The maximum skew is measured between any two components32 rather than between connectors. To correctly evaluate clock skew, the system designer must take into account clock distribution on the add-in card which is specified in Section 4.4.
Table 4-8: Clock Skew Parameters
Symbol 3.3V Signaling 5V Signaling Units
Vtest 0.4 Vcc 1.5 V
Tskew 2 (max) 2 (max) ns
CLK [@ Device #1]
CLK [@ Device #2]
Vih
Tskew
Tskew Vil
Vih
Vtest
Tskew
Vtest Vil
A-0187
Figure 4-10: Clock Skew Diagram
4.3.2. Reset
The assertion and deassertion of the PCI reset signal (RST#) is asynchronous with respect to CLK. The rising (deassertion) edge of the RST# signal must be monotonic (bounce free) through the input switching range and must meet the minimum slew rate specified in Table 4-5. The PCI specification does not preclude the implementation of a synchronous RST#, if desired. The timing parameters for reset are listed in Table 4-6 with the exception of the Tfail parameter. This parameter provides for system reaction to one or both of the power rails going out of specification. If this occurs, parasitic diode paths could short circuit
32The system designer must address an additional source of skew. This clock skew occurs between two components that have clock input trip points at opposite ends of the Vil - Vih range. In certain
circumstances, this can add to the clock skew measurement as described here. In all cases, total clock skew must be limited to the specified number.
active output buffers. Therefore, RST# is asserted upon power failure in order to float the output buffers.
The value of Tfail is the minimum of:
500 ns (maximum) from either power rail going out of specification (exceeding specified tolerances by more than 500 mV)
100 ns (maximum) from the 5V rail falling below the 3.3V rail by more than 300 mV.
The system must assert RST# during power up or in the event of a power failure. In order to minimize possible voltage contention between 5V and 3.3V parts, RST# must be asserted as soon as possible during the power up sequence. Figure 4-11 shows a worst case assertion of RST# asynchronously following the "power good" signal.33 After RST# is asserted, PCI components must asynchronously disable (float) their outputs but are not considered reset until both Trst and Trst-clk parameters have been met. The first rising edge of RST# after power-on for any device must be no less than Tpvrh after all the power supply voltages are within their specified limits for that device. If RST# is asserted while the power supply voltages remain within their specified limits, the minimum pulse width of RST# is Trst.
Figure 4-11 shows RST# signal timing.
The system must guarantee that the bus remains in the idle state for a minimum time delay following the deassertion of RST# to a device before the system will permit the first assertion of FRAME#. This time delay is included in Table 4-6 as Reset High to First FRAME# assertion (Trhff). If a device requires longer than the specified time (Trhff) after the deassertion of RST# before it is ready to participate in the bus signaling protocol, then the device's state machines must remain in the reset state until all of the following are simultaneously true:
RST#is deasserted.
The device is ready to participate in the bus signaling protocol.
The bus is in the idle state.
IMPLEMENTATION NOTE
Reset
An example of a device that could require more than Trhff to be ready to participate in the bus signaling protocol is a 66-MHz device that includes a Phase-Locked Loop (PLL) for distribution of the PCI clock internally to the device. The device may inhibit clocks to the PCI interface until the PLL has locked. Since the PLL could easily require more than Trhff to lock, this could result in the clocks being enabled to the PCI interface of this device in the middle of a burst transfer between two other devices. When this occurs, the 66-MHz device would have to detect an idle bus condition before enabling the target selection function.
Some PCI devices must be prepared to respond as a target Trhff time after RST#deasserts.
For example, devices in the path between the CPU and the boot ROM (not expansion ROM) must be prepared to respond as a target Trhff time after RST# deasserts.
All other devices must be prepared to respond as a target not more than Trhfa after the deassertion of RST#. It is recommended that the system wait at least Trhfa following the deassertion of RST# to a device before the first access to that device, unless the device is in the path between the CPU and the boot ROM or the system knows that the device is ready sooner.
Software that accesses devices prior to the expiration of Trhfa must be prepared for the devices either not to respond at all (resulting in Master-Abort) or for the devices to respond with Retry until the expiration of Trhfa. At no time can a device return invalid data.
Devices are exempt from the Maximum Retry Time specification and the target initial latency requirement until the expiration of Trhfa.
IMPLEMENTATION NOTE
Trhfa
Devices are encouraged to complete their initialization and be ready to accept their first cycle (generally a Configuration Read cycle) as soon as possible after the deassertion of RST#. Some system implementations will access devices prior to waiting the full value of Trhfa, if they know in advance that all devices are ready sooner. For example, a system with no PCI slots would only need to wait for the initialization requirements of the embedded devices.
Similarly, an intelligent add-in card that initialized its own embedded PCI devices would only need to wait for the initialization requirements of those devices.
In some cases, such as intelligent add-in cards, the add-in card designer must select devices that initialize in less than the full value of Trhfa. For example, suppose an intelligent add-in card is not ready to respond as a target to the first Configuration transaction from the host CPU until after the local CPU has configured the local devices. In this case, the local devices must initialize fast enough to enable the local CPU to complete its initialization in time for the first access from the host CPU.
33 Component vendors should note that a fixed timing relationship between RST# and power sequencing cannot be guaranteed in all cases.
POWER
Figure 4-11: Reset Timing 34
Refer to Section 3.8.1 for special requirements for AD[63::32], C/BE[7::4]#, and PAR64 when they are not connected (as in a 64-bit add-in card installed in a 32-bit connector).