EXCEPCIONES POTESTATIVAS: LAS EXCLUSIONES DEL ARTÍCULO 4.

The CPRI v6.0 IP core provides multiple calibration features to support compliance with the CPRI v6.0 Specification..

• If you turn on Enable single-trip delay calibration in the CPRI v6.0 parameter editor, supports single- trip delay calibration using the DELAY_CAL_STD_CTRL1, DELAY_CAL_STD_CTRL2,

DELAY_CAL_STD_CTRL3, DELAY_CAL_STD_CTRL3, DELAY_CAL_STD_CTRL4, DELAY_CAL_STD_CTRL5, and DELAY_CAL_STD_STATUS registers.. You can connect the IOPLL and DPCU blocks that Altera provides

with the CPRI v6.0 IP core to ensure correct calibration results.

• If you turn on Enable round-trip delay calibration in the CPRI v6.0 parameter editor, supports round-trip delay calibration using the DELAY_CAL_RTD register.

• In all supported device families, increases the consistency of the round-trip delay using the

XCVR_BITSLIP register.

Single-Trip Delay Calibration

The CPRI v6.0 IP core provides an optional mechanism to support calibrating the total delay through a CPRI master and slave on the downlink in a single hop.

If you turn on Enable single-trip delay calibration in the CPRI v6.0 parameter editor, the CPRI v6.0 IP core and IOPLL and dynamic phase control unit (DPCU) blocks work together to adjust the delay through the RE slave Rx path in response to information about the delay through the REC or RE master Tx path.

3-56 Multi-Hop Delay Measurement _2016.07.22UG-20008

Figure 3-39: Downlink Slave Delay Adjustment for Single-Trip Delay Calibration

Master TX FIFO Slave RX FIFO

CPRI Link SAPm SAPs Before Calibration After Calibration 0s 0s Added Delay Desired Latency Before Calibration After Calibration 0s 0s Reduced Delay Desired Latency Example 1: Example 2:

The feature introduces the new delay to maintain a single-trip delay measurement as close as possible to the desired single-trip delay you provide to the CPRI v6.0 IP core. The application can also provide Tx path delay information that is appropriate for other use scenarios. For example, you might want to adjust the latency to the synchronization SAP to compensate for the IQ mapper requirements in your system. Refer to the Altera wiki Latency Formula and Calculation Example page.

Figure 3-40: Single-Trip Delay Does Not Affect Link Delay

Master TX FIFO Slave RX FIFO

HSSI SAPm SAPs Before Calibration After Calibration 1 After Calibration 2 Fixed Round- Trip Delay Downlink Delay is Guaranteed Fixed to User Input Value

Slave TX FIFO Master RX FIFO

HSSI

SAPm

The cal_cycle_delay and cal_step_delay fields of the DELAY_CAL_STD_CTRL2 register in the CPRI link

slave hold the anticipated delay that you program. The cal_current_delay field of the

DELAY_CAL_STD_STATUS register in the CPRI link slave holds the total actual variable delay measurement

in the single trip from the synchronization SAP in the CPRI link master to the synchronization SAP in the current CPRI link slave. You can manually specify a consistency check whenever you want, or you can specify that the IP core should run a consistency check once every hyperframe.

If you turn on single-trip delay calibration by setting the cal_en bit in the DELAY_CAL_STD_CTRL1 register,

the single-trip calibration feature is active. The user programs the cal_cycle_delay and cal_step_delay UG-20008

2016.07.22 Single-Trip Delay Calibration 3-57

Functional Description Altera Corporation

fields with the number of whole and fractional cpri_clkout cycles of single-trip variable delay that the

system requires. After each consistency check, the CPRI v6.0 slave IP core adjusts the Rx delay to

compensate for mismatches between the programmed, required single-trip delay and the actual single-trip variable delay recorded in the cal_current_delay register field. The delay adjustment mechanism is

dynamic phase shifting of the cpri_coreclk.

The slave IP core requires the master IP core measured Tx delay information to calculate the

cal_current_delay value. The master IP core sends this information to its downlink slave by one of two

possible mechanisms. You program the master IP core DELAY_CAL_STD4 register to specify whether the

master sends this information in the incoming hyperframe (and at which location in the hyperframe) or the system writes it in the dedicated slave IP core DELAY_CAL_STD_CTRL5 register. You program the slave

IP core DELAY_CAL_STD3 register to specify whether the slave receives this information in the incoming

hyperframe (and at which location in the hyperframe) or the system writes it in the dedicated slave

DELAY_CAL_STD_CTRL5 register. If both CPRI master and slave are CPRI v6.0 IP cores, and the register

values in the CPRI link master and slave do not match, the single-trip delay calibration does not function correctly. If the CPRI master is not a CPRI v6.0 IP core, the CPRI slave must receive the correct informa‐ tion in the programmed register or hyperframe location.

Related Information

Altera wiki CPRI IP v6 Latency Formula and Calculation Example

Provides information about how to use the single-trip delay calibration feature.

Single-Trip Latency Measurement and Calibration Interface Signals

Table 3-18: Single-Trip Latency Measurement and Calibration Interface Signals

If you turn on Enable single-trip delay calibration in the CPRI v6.0 parameter editor, the single-trip latency measurement and calibration interface is available. This interface is designed to connect to the DPCU block that helps implement single-trip delay calibration.

All interface signals are clocked by the reconfig_clk clock.

Signal Name Direction Description

cal_status[1:0] Input Status information from DPCU to CPRI v6.0 IP core.

cal_ctrl[15:0] Output Control information from CPRI v6.0 IP core to DPCU.