FACTORES PRINCIPALES QUE INTERVIENEN EN LA GERMINACIÓN

The best MBE Ge/SiC diodes considered within this Chapter in terms of forward resis- tance, blocking voltage, leakage current and ideality factor were those grown to a thickness of between 300 and 500 nm, at the higher temperature of 500o_{C. In this Section, these}

high temperature Ge/SiC diodes, which were formed from intrinsic, p-type and n-type Ge, will be compared to SiC metal/semiconductor Schottky Barrier Diode results taken from the literature.

6.3.4.1 The Model Diodes

The diodes considered here [91–94] originate from four different groups and feature devices designed for high voltage blocking and those rated at a lower voltage but with a much lower specific-on resistance. The results are showed in Figure 6.16.

As suggested in Section 2.4 and Appendix A.6, a trade off exists between blocking voltage and series resistance due to the thickness of the epi-layer. This is shown in its extreme when, 10 years ago, the then brand new material, SiC, was being pushed to its limits. Singh et al [94]produced a 5 kV SBD, formed from a 50 µm epitaxial SiC layer doped at 5 ×1014 _cm−3_{. The authors of this work claimed a specific on-resistance of}

17 mΩcm2_{; however, a simple fit to their data using the ideal diode equation suggests}

that a figure of 45 mΩcm2_{, may be more accurate. Made using a Ni contact, this is one}

6.3 Electrical Analysis of Heterojunction Layers

(a) Ideality Factor and SBH Profiles.

(b) Resistance Comparisons.

Figure 6.16: A comparison between the Ni/Ge/SiC diodes and SiC diodes found in the literature [91–94].

6.3 Electrical Analysis of Heterojunction Layers

not shown here, was a 10 kV device produced from a massive 115 µm epitaxial SiC layer doped at 5×1014 _cm−3_{. The price paid for this was the specific on-resistance, which was}

up at 97.5 mΩcm2_.

At the other end of this trade-off is the work by Chang et al [92], who used a 10µm epitaxial SiC layer doped at 3 ×1014 _cm−3_{, - very similar substrates to those used to}

produce the Ge/SiC heterojunction diodes. Conducting a study that optimised the use of floating metal rings to distribute the electric field at the SiC surface, they achieved a breakdown close to 1 kV for a Ni/SiC diode at a specific on-resistance estimated to be as low as 1.75 mΩcm2_{. Similarly impressive on-resistance values were achieved for titanium}

and aluminium contacts, and these are also shown in the Figures.

Two other SBDs are presented in Figure 6.16, the details of which are listed in 6.3. Vassilevski et al [91] produced a 3.4 kV SBD from a 20µm epi-layer at 16 mΩcm2_{. Finally,}

for a comparison across polytypes, a 6H-SiC SBD produced by La Via et al is also included. Their 4µm epi-layer produced an on-resistance of 17 mΩcm2_{, but breakdown is not stated.}

Diode nGe pGe iGe Ni [94] Ni [91] Ni [93] Ni [92] Ti [92] Al [92]

Epi (µm) 10 10 10 50 20 4 10 10 10

EpiND(cm−3_{) 1.4e15 1.4e15 1.4e15 7e14 3e15 2.8e15 3.5e15 3.5e15 3.5e15}

VB (V) 250 250 – 5k 3.4k – 900 850 600

Ron,sp (mΩcm2_{) 18.3 17.3 12.2 17/45* 16* 17* 1.75* 3* 1.8*}

η 1.039 1.047 1.026 1.1 1.1* 1.07 1.163 1.094 1.176

ΦB,n (eV) 1.094 1.127 1.086 1.41 1.4 1.30 1.38 0.99 0.77

ρc (Ωcm2_{) 5e-4 1.e-3 – – – 4e-5 – – –}

Table 6.3: The best Ge/SiC heterojunction diodes compared to Ni/SiC SBDs taken from the literature as follows: a) Singh [94], b) Vassilevski [91] c) La Via [93] d) Chang [92]. VB is the breakdown voltage, Ron,sp the specific on-resistance, η the ideality

factor, ΦB,n the SBH andρc the contact resistivity. Parameters with the * are estimated

from fitting parameters.

6.3 Electrical Analysis of Heterojunction Layers

do not look out of place amongst these metal-semiconductor devices. All three Ni/Ge/SiC structures produce an ideality factor below 1.05, lower than all the diodes taken from the literature. This indicates that thermionic emission dominates the transport of carriers over the heterojunction interface, as predicted by the diode equation of Equation 3.12. The best heterojunction diode has an on resistance of just 12.2 mΩcm2_{, which compares}

favourably with La Via [93] and Singh’s [94] diodes, though they fall behind the other diodes employing a 10µm epi layer. This is however in light of a number of imperfections such as grain boundaries and poor contact resistivity, the improvement of which will lower this resistance further. Considering the ohmicity of the contacts, the p- and n-type Ge/SiC devices are respectively 2 and 1 orders of magnitude higher than that reported by La Via et al [93]. Having proven that high temperature layers produce good diodes, experimentation with post MBE anneals is a future project that will produce better Ni/SiC back contacts and Ni/Ge front contacts.

However, the heterojunction diodes simply cannot compete in terms of breakdown volt- age. Proven in extensive studies on oxide/poly-Si [108–110], such rough surfaces and the large number of grain boundaries promote the build up of an electric field at the surface, diminishing breakdown and causing leakage through the oxide layer. The Ge/SiC struc- tures also suffer from their very simple structure. For ease of fabrication, these devices were formed from very simple mesa-etched dots that required just one photolithographic mask level to produce. The devices from [91, 92, 94] in Table 6.3 involve the use of edge termination, whilst [91] also employs surface passivation. Boron implants in [91, 94] are used to form their junction termination extensions (JTE) adding complexity, mask levels and cost. The lack of such an edge termination in the Ge/SiC devices explains the low breakdown values as the spreading of the electric field across the surface is unabated and the devices are allowed to breakdown at the weakest point, the contact edge. A potential

6.3 Electrical Analysis of Heterojunction Layers

device structure including JTEs is shown in Figure 6.17. The potential is clear in these structures to block a significant voltage, as 250 V is not insignificant. What is also greatly encouraging, is the results of Si/SiC heterojunction diodes [19,20], that managed to block 1600 V using the same 10 µm SiC epitaxial layers but with JTEs and field plates. It seems likely that Ge could reach very similar levels given these more advanced processing techniques.

Figure 6.17: A heterojunction SBD with Junction termination extensions.

There are two further mitigating points for the breakdown results. The barrier height for these devices is around 75 % that of a Ni/SiC Schottky diode and the effect that this has can be witnessed in Table 6.3. Chang et al’s aluminium and titanium diodes with barrier heights of 0.77 and 0.99 eV respectively give rise to breakdown voltages of 600 and 800 V. Given a barrier height of 1.1 eV, the 800 V figure should be a minimum figure achievable by the Ge/SiC diodes. However, the final mitigating point is that the use of Ge most likely has an impact on the breakdown values as well, being that it has a critical field only one tenth that of SiC.

6.3 Electrical Analysis of Heterojunction Layers

Of course, with funding, facilities and time, exploration into the use of post deposition polishing and edge termination techniques ought to be explored to maximise the break- down values of these devices. However, one reasonably cheap way to achieve such a result will be to employ the floating metal ring edge termination, which features in Chang et al’s work [92]. Claiming an increase in breakdown voltage of 142 %, their very simple design looks possible to implement in only one mask layer.