Fatigue growth of interlaminar cracks

During SLEEP or IDLE modes, depending upon the configuration, the operation of the A/D converter is possible. These modes are useful for minimizing conversion noise because the digital activity of the CPU, buses, and other peripherals is minimized.

Operation in SLEEP mode without RC A/D clock – If the internal RC clock generator is not used, when the device enters SLEEP mode, all clock sources to the module are shut down.

If SLEEP occurs in the middle of a conversion, the conversion is aborted. The converter will not resume a partially completed conversion on exiting from SLEEP mode. Register contents are not affected by the device entering or leaving SLEEP mode.

Operation in SLEEP mode with RC A/D clock – If the A/D clock source is set to the internal RC oscillator (ADRC=1), the A/D module can operate during SLEEP mode. This eliminates digital switching noise. When the conversion is completed, the CONV bit will be cleared and the result loaded into the RAM buffer.

If the interrupt is enabled ADIE=1 (IEC0<11>), the device will wake-up from SLEEP when the A/D interrupt occurs ADIF=1 (IPS0<11>). The interrupt service routine will be carried out if the A/D’interrupt is greater than the current CPU priority. Otherwise, the device returns to SLEEP mode.

If the A/D interrupt is not enabled, the A/D module will then be turned off while the ADON bit remains set.

To minimize the effects of digital noise on the A/D module operation, the user shoud select a convesrion trigger source before the microcontroller enters SLEEP mode. The control bits SSRC<2:0>=111 are set befor the PWRSAV instruction.

Attention!!!

If the operation of the A/D converter during SLEEP mode is required, the user has to select the internal RC clock generator (ADRC=1)

Operation during IDLE mode – If the control bit ADIDL (ADCON1<13>) is cleared, the A/D module will continue normal operation in IDLE mode. If the A/D interrupt is enabled (ADIE=1), the device will wake-up from IDLE mode when the A/D interrupt occurs. The A/D interrupt service routine will be carried out if the A/D interrupt is greater than the current CPU priority. Otherwise, the device returns to IDLE mode.

If A/D interrupt is disabled, the A/D module will be turned off while the ADON bit remains set.

If the control bit ADIDL is set, the module will stop in IDLE mode. If the device enters IDLE mode in the middle of a conversion, the conversion is aborted. The converter will not resume a partially completed conversion on exiting from IDLE mode.

Attention!!!

A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion in prgress is aborted. All pins will be configured as analogue inputs. The RAM buffer will contain unknown data.

Fig. 7-10a Pinout of dsPIC30F4013.

Fig. 7-10b Pinout of dsPIC30F6014A.

Finally, the desriptions of the A/D module control registers are presented.

name ADR

15-12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State

ADBUF0 0x0208 - ADC DATA BUFFER 0 0x0uuu

ADBUF1 0x0208 - ADC DATA BUFFER 1 0x0uuu

Table 7-2 Description of the RAM buffer registers.

NOTE: Unimplemented bits read "0".

name ADR 15 14 13

12-10 9 8 7-5 4-3 2 1 0 Reset

State ADCON1 0x02A0 ADON - ADIDL - FORM<1:0> SSRC<2:0> ASAM SAMP CONV 0x0000 Table 7-3 Description of the configuration register ADCON1

ADON – A/D operating mode bit

(ADON=1 A/D converter module is operating, ADON=0 A/D converter is off)

ADIDL – Stop in IDLE mode bit (ADIDL=1 discontinue module operation when device enters

IDLE mode, ADIDL=0 continue module operation in IDLE mode) FORM<1:0> - Data output format bits

00 – integer

01 – signed integer 10 – fractional

11 – signed fractional

SSRC<2:0> - Conversion trigger source select bit

000 – clearing SAMP bit ends sampling and starts conversion 001 – active transition on INTO pin ends sampling and starts conversion

010 – general purpose timer3 compare ends sampling and starts conversion

011 – motor control PWM interval ends sampling and starts conversion 101...110 – reserved

111 – automatic mode

ASAM – A/D sample auto-START bit

SAMP – A/D sample enable bit (SAMP=1 at least one A/D sample/hold amplifier sampling,

SAMP=0 sample/hold amplifiers are holding) DONE – A/D conversion status bit

(DONE=1 A/D conversion is done, DONE=0 A/D conversion is in progress)

NOTE: Unimplemented bits read "0". Table 7-4 Description of the configuration register ADCON2

VCFG<2:0> - Voltage reference configuration bit 000 - VREFH =AVDD, VREFL=AVSS

001 - VREFH= External VREF+ pin, VREFL=AVSS 010 - VREFH =AVDD, VREFL=External VREF- pin

011 - VREFH= External VREF+ pin, VREFL=External VREF- pin 1xx - VREFH =AVDD, VREFL=AVSS

CSCNA - Scan input selections for CH0+ S/H input for MUX A input multiplexer setting bit

BUFS - Buffer full status bit

Only valid when BUFM=1 (ADRES split into 2 x 8-word buffers) BUFS=1 A/D is currently filling higher buffer 0x8-0xF, BUFS=0 A/D is currently filling lower buffer 0x0-0x7

SMPI<3:0> - Sample/convert sequences per interrupt selection bits 0000 - interrupts at the completion of conversion for each sample/convert sequence

0001 - interrupts at the completion of conversion for each 2nd sample/convert sequence

...

1110 - interrupts at the completion of conversion for each 15th sample/convert sequence

1111 - interrupts at the completion of conversion for each 16th sample/convert sequence

BUFM - Buffer mode select bit (BUFM=1 Buffer configured as two 8-word buffers

ADCBUF(15...8), ADCBUF(7...0),

BUFM=0 Buffer configured as one 16-word buffer ADCBUF(15...0)) ALTS - Alternate input sample mode select bit

(ALTS=1 alternate sampling enabled, ALTS=0 always use MUX A input) Table 7-5 Description of the configuration register ADCON3

SAMC<4:0> - Auto sample time bits 00000 - 0 TAD

00001 - 1 TAD ...

11111 - 31 TAD

ADRC - A/D conversion clock source bit (ADRC=1 A/D internal RC clock, ADRC=0 Clock derived from system clock)

ADCS<5:0> - A/D conversion clock select bits 000000 - TCY/2 * (ADCS<5:0> + 1)=TCY/2 000001 - TCY/2 * (ADCS<5:0> + 1)=TCY ...

111111 - TCY/2 * (ADCS<5:0> + 1)=32*TCY

NOTE: Unimplemented bits read "0".

name ADR

15-13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reset State ADCHS 0x02A6 - CH0NB CH0SB<3:0> - - - CH0NA CH0SA 0x0000 Table 7-6 Description of the ADCHS configuration register

CH0NB - Channel 0 negative input select for MUX B multiplexer setting bit (CH0NB=1 input AN1 selected, CH0NB=0 input VREF- selected)

CH0SB<3:0> - Channel 0 positive input select for MUX B multiplexer setting bit

CH0NA - Channel 0 negative input select for MUX A multiplexer setting bit (CH0NA=1 input AN1 selected, CH0NA=0 input VREF- selected)

CH0SA<3:0> - Channel 0 positive input select for MUX A multiplexer setting bit

ADPCFG 0x02A8 PCFG<15:0> 0x0000 Table 7-7 Description of the ADPCFG configuration register

PCFG<15:0> - Analogue input pin configuration control bits (PCFG(i)=1 pin ANi configured as digital I/O pin,

PCFG(i)=0 pin ANi configured as analogue input pin)

name ADR 15-0 Reset state

ADCSSL 0x02AA ADC Input scan select

register 0x0000

Table 7-8 Description of the ADCSSL configuration register

ADCSSL<15:0> - A/D input pin scan selection bits