Flujo de caja y VAN

There may be occasions on which not all the inputs or outputs of a component are needed. Therefore these inputs and outputs would be connected to the supply rails or left unconnected. To illustrate this, let us invent a ‘universal’ gate. This gate has three inputs and two outputs. The two outputs are the AND and OR functions. Two of the inputs are the normal logical inputs for an AND or OR function. The third input indi-cates whether the outputs are to be inverted. Thus the gate implements the AND, OR, NAND and NOR functions. A VHDL description of this gate follows.

entity universal is

port (x, y, invert : in BIT; a, o : out BIT);

end entity universal;

architecture univ of universal is begin

a <= (y and (x xor invert)) or (invert and not y);

o <= (not x and (y xor invert)) or (x and not invert);

end architecture univ;

It is left as an exercise for the reader to derive the logic equations. Note that the two signal assignments occur concurrently, not sequentially. We will return to this in the next chapter. To use this gate as an AND gate, we would set the invert input to ‘0’ and leave the o output unconnected. This is done using a value instead of a signal and by using the reserved word open again:

u0 : entity WORK.universal(univ) port map (x, y, '0', a, open);

Outputs can be left unconnected, but inputs may be left open only if a default value has been specified in the entity declaration or the component declaration, as for generics:

entity universal is port (x, y : in BIT;

invert : in BIT := '0';

a, o : out BIT);

end entity universal;

The following instantiation would now be legal:

u0 : entity WORK.universal port map (x, y, open, a, open);

48 Combinational logic using VHDL gate models

3.7 Testbenches

If we wish to simulate our circuit to verify that it really does work as expected, we need to apply some test stimuli. We could, of course, write out some test vectors and apply them, or, more conveniently, write the test data in VHDL. This type of VHDL model is often known as a testbench. Testbenches have a distinctive style. Below is a testbench for a two-input AND gate.

entity TestAnd2 is end entity TestAnd2;

architecture io of TestAnd2 is signal a,b,c : BIT;

begin

g1: entity WORK.And2(ex2) port map (x=>a, y=>b, z=>c);

a<= '0', '1' after 100 NS;

b<= '0', '1' after 150 NS;

end architecture io;

Because this is a testbench, i.e. a description of the entire world that affects the model we are testing, there are no inputs or outputs in the entity. This is characteristic of test-benches. The description in the architecture consists of an instance of the circuit we are testing, together with a set of input stimuli. Signals corresponding to the input and out-put ports of the circuit are also declared. Inside the body of the architecture one instance of the circuit is created.

This is a very simple example of a testbench. It provides sufficient inputs to run a simulation, but the designer would need to look at the simulation results to check that the circuit was functioning as intended. VHDL has the richness of a programming lan-guage. Therefore a testbench could be written to check simulation results against a file of expected responses or to compare two versions of the same circuit.

3.8 Configurations

Here is another description of a two-input AND gate in VHDL:

architecture ex3 of And2 is

signal xy : BIT_VECTOR(0 to 1);

begin

xy <= x&y;

with xy select

z <= '1' when "11", '0' when others;

end architecture ex3;

Configurations 49

We will explain the constructs in the next chapter. We now have two different architectures (ex1 from Section 3.1 and ex3) associated with the same entity.

(ex2 from Section 3.5 is the same as ex1, but with a delay, and hence has a different entity declaration.) In the previous examples, the architecture name was explicitly stated, but it can be omitted. If an entity has only one architecture, there is no ambigu-ity – both the following have the same meaning:

g1: entity WORK.Not1(ex1) port map (a, p);

g1: entity WORK.Not1 port map (a, p);

If, however, there were two or more architectures in the same file, then in the second case, by default, we would automatically use the last architecture. Suppose that we wish to have more control over exactly which architecture to use. With direct instan-tiation, there is no difficulty. With the alternative style, however, there needs to be an explicit statement – the configuration specification. For example, the testbench example of the last section could be written as:

architecture alternate of TestAnd2 is component A2 is

port (x, y : in BIT; z: out BIT);

end component A2;

for all : A2 use entity WORK.And2(ex2);

signal a,b,c : BIT;

begin

g1: A2 port map (x=>a, y=>b, z=>c);

end architecture alternate;

By using the for . . . use construct we can choose which architecture to use.

With simple testbenches, the style shown above may be appropriate. For complex mod-els, with several levels of hierarchy, it is often more appropriate to use a configurationunit. A configuration declaration for the original testbench shown might be:

configuration Tester1 of TestAnd2 is for io

for g1 : And2

use entity WORK.And2(ex1);

end for;

end for;

end configuration Tester1;

The complete model therefore consists of the entity and architecture of the And2 gate, the entity and architecture of the testbench and the configuration. There are other ways to write configurations, but this style requires one configuration for the entire design. Note that now we would not include a for . . . use statement within the testbench.

50 Combinational logic using VHDL gate models

It is also possible to use configurations to map port and generic names. Suppose the testbench were written as:

architecture remapped of TestAnd2 is component MyAnd2 is

generic (dly : DELAY_LENGTH);

port (in1, in2 : in BIT; out1: out BIT);

end component MyAnd2;

signal a,b,c : BIT;

begin

g1: MyAnd2 generic map (6 NS) port map (a, b, c);

end architecture remapped;

We would write the configuration as:

configuration Tester2 of TestAnd2 is for remapped

for g1 : MyAnd2

use entity WORK.And2(ex2) generic map (delay => dly);

port map (x => in1, y => in2, z => out1) end for;

end for;

end configuration Tester2;

This is a ‘board–socket–chip’ analogy, where the configuration is used to map between arbitrary internal and external names.

A different style of configuration has one configuration per entity, e.g.:

configuration And2Con of And2 is for ex1

end for;

end configuration And2Con;

This selects the architecture for an entity. For the testbench example we then have a configuration such as:

configuration Tester3 of TestAnd2 is for remapped

for g1 : MyAnd2

use configuration WORK.And2Con;

end for;

end for;

end configuration Tester3;

This approach requires a greater number of configuration units, but each unit is sim-pler. Configurations are important for controlling projects involving a number of design-ers. For designs done by a single designer using a single FPGA, either configuration statements in each architecture or a single configuration unit is likely to be sufficient.

Exercises 51

Summary

A VHDL model has an entity part, which is a description of the interface of the model, and one or more architecture parts, which describe the functionality of the model. VHDL models should use meaningful identifiers and include comments. In this respect, writing good VHDL is much like writing good software. Netlists of VHDL models can be constructed by instantiating those models. There are a number of alter-native ways to instantiate models. Parameters may be passed to models using generics. The reserved word open is used to specify an unconnected port or defaulted generic. VHDL models may be exercised using testbenches, also written in VHDL. Configuration statements and units are used to associate architectures with particular instances of models.

Further reading

The definition of VHDL is contained in the Language Reference Manual (LRM). This can be bought from the IEEE. Every college or university library should have a copy!

There are a number of VHDL books available, but even some recent editions cover only the 1987 standard.

Exercises