6 Acerca de la poderosa realidad fílmica: obstrucciones y
6.2 Entre lo formal y la narración
Following the frequency de-interleaving, the cells will be in the correct order to reverse the function of the frame builder, and so extract the L1 signalling and the PLPs.
10.4.2.1
Extraction of the PLPs
The PLP (or PLPs) to be received should be extracted based on the PLP_START and PLP_NUM_BLOCKS parameters as described in clause 7.2.3.2 of [i.1]. These parameters are carried in the P2 symbol(s) and may also be signalled using in-band signalling (see clause 10.4.2.4).
The specification describes how the slices or sub-slices of the PLPs should be placed immediately one after the other, with the common PLPs starting from the first cell not used for L1 signalling, followed immediately by the type 1 and then type 2 PLPs.
However, this should not be assumed by the receiver, since future applications may introduce other uses for the cells, which might involve inserting cells between PLPs, between sub-slices or between the PLPs of different types. In all cases the locations as signalled by PLP_START and PLP_NUM_BLOCKS will be correct.
Any data cells which are not allocated to one of the PLPs being decoded should be discarded.
10.4.2.2
Extraction of the L1 signalling cells
The L1 signalling cells are carried in the P2 symbols as described in clause 8.5.3 of [i.1]. When the cells are extracted, the zig-zag order should be undone; this can be considered as a de-interleaving process, and should be implemented as part of the frequency de-interleaver as described in clause 10.4.1. This is both an efficient use of memory and also corresponds to the assumptions in the receiver buffer model.
Since L1-pre signalling is mapped to 1 840 BPSK symbols in NP2 P2 symbols as described in clause 8.3.5 of [i.1], the received signal for L1-pre signalling should be obtained from the first 1 840/NP2 BPSK symbols in each P2 symbol. The process is similar for the L1-post signalling cells, except that the receiver needs to determine how many there are; this information is signalled directly by the L1-pre signalling parameter L1_POST_SIZE. In normal reception, this will already be known since it is statically configurable. However, on first acquisition, or if the value has changed since the frequency was last visited, the L1-pre signalling will need to be decoded before the L1-post cells can be extracted.
NOTE: The field L1_POST_SIZE is provided for convenience, but the same information could be deduced from the field L1_POST_INFO_SIZE as described in clause 10.5.7.1.
10.4.2.3
Timing of L1 and PLP extraction and decoding in the P2 symbols
The timing of signal flows during the P2 symbols can be quite critical, because of the way each of the L1-pre, L1-post and PLP extraction and decoding depends on the previous stage.
Figure 92 shows a timeline of the process, with the time taken for each stage according to the receiver buffer model. Some of the stages can take place in parallel; in particular the FEC chain can be receiving input cells, outputting decoded cells and decoding a block at the same time.
As can be seen, the critical path comprises extracting the L1-pre cells, decoding the L1-pre, outputting the decoded L1-pre bits, extracting the L1-post cells for the first block, Npost_FEC_block-1 intermediate stages, and finally decoding and
The "extracting cells" stage includes soft demapping (see clause 10.5.1). The model assumes that this can be done at a maximum rate of RS=1/T for the L1-post, which might use up to 64-QAM. For the L1-pre, BPSK is always used, so
soft-demapping is trivial. In this case the model assumes that the demapping can be done eight times faster.
Implementers should therefore provide a simple 1-D demapper for BPSK capable of working at this rate, rather than using the full 2D demapper which is unlikely to be able to operate quickly enough.
In the figure, the intermediate stages are limited by the decoding time for a FEC block. However, in another
configuration the time taken to extract (and soft-demap) the cells of the next block might be longer than the decoding time, particularly if a low-order constellation is used for the L1-post.
Figure 92: Timeline for extraction and FEC decoding for the P2 symbols We can therefore calculate the complete time for L1 extraction and decoding:
(N
)
(T
T
)
T
K
T
T
T
R
T
T
extract post FEC block extract decode decode sig postcell L
8
,
max
1
8
200
2025
8
1840
_ _ _ 1=
+
+
+
+
−
×
+
+
,where
T
extract=N_MOD_PER_BLOCK×T
andcell decode
R
T
=2025
are the times to demap and decode one L1-post FEC block, respectively.10.4.2.4
Use of in-band dynamic signalling
10.4.2.4.1
Interleaving over one T2 frame or less
The T2 receiver can obtain L1-dynamic signalling from in-band signalling as well as P2 symbols. The in-band signalling is carried in the PADDING field of the first BBFRAME of each PLP, when IN-BAND_FLAG field in L1-post signalling, defined in EN 302 755 [i.1], is set to '1' and one Interleaving Frame is mapped to one T2-frame (i.e. the values for PI and IJUMP for the current PLP are both equal to 1; see clauses 6.5 and 8.2 of [i.1]).
If NUM_OTHER_PLP_IN_BAND field in the in-band signalling is set to '0', the in-band signalling of a PLP carries only its own L1 dynamic information. On the other hand, if the NUM_OTHER_PLP_IN_BAND field is larger than '0', the in-band signalling of a PLP carries L1 dynamic information of other PLPs as well as its own information, for shorter channel switching time. The in-band signalling in T2-Frame n carries L1 dynamic information of T2-frame n + 1. Therefore, the T2 receiver can obtain the L1-dynamic signalling of the next T2-frame through the in-band signalling received in the current T2-frame and can decode PLPs of the next T2-frame without decoding the P2 symbols of the next frame.
10.4.2.4.2
In-band signalling when interleaving over multiple T2 frames
When multi-frame interleaving is used, i.e. PI > 1 so that one Interleaving Frame is mapped to more than one T2 frame, in-band L1-dynamic signalling can still be used. In this case the in-band signalling of a PLP carries only its own L1 dynamic information, and the information applies to the T2 frames to which the next Interleaving Frame is mapped. The information applies to the next Interleaving Frame because the receiver cannot decode any of the FEC blocks and recover the BBFRAME containing the in-band L1 until the whole Interleaving Frame has been received; any
information for the current Interleaving frame would be decoded too late to be of any use.
A loop is used to carry dynamic L1 information for each of the PI frames to which the next Interleaving Frame will be mapped. This is necessary because the BBFRAMEs do not belong to any one T2 frame so cannot meaningfully signal only the next T2 frame's parameters. Furthermore, there might only be one BBFRAME in the whole Interleaving Frame.
There is therefore only one place in the interleaving frame in which the in-band signalling can be sent: the first BBFRAME of the Interleaving Frame.
Carrying in-band L1 dynamic information for other PLPs in this case would have made the signalling excessively complicated and was not thought to be worthwhile.
Note that in-band signalling is not mandatory in this case, since it requires extra memory in the modulator and incurs extra end-to-end delay.
10.4.2.4.3
In-band signalling for PLPs not present in every T2-frame
In-band signalling can also be used for PLPs which are not present in every T2 frame. In this case, the signalling applies to the T2 frame to which the next Interleaving Frame is mapped. If each Interleaving Frame is mapped to one T2 frame, the signalling therefore applies to the next T2 frame to which the PLP is mapped. For multi-frame interleaving, the dynamic information is signalled in a loop for each of the T2 frames to which the next interleaving frame is mapped. Again, in-band signalling is not mandatory in this case because of the implications for memory in the modulator and end-to-end delay.
10.4.2.4.4
Reading the P2 symbols on reconfiguration
It can be signalled in the in-band signalling where the configuration (i.e. the contents of the fields in the L1-pre signalling or the L1-post signalling) will change in a way that affects the PLPs referred to by this in-band signalling field. This is indicated by PLP_L1_CHANGE_COUNTER field in the in-band signalling of 'In-band type A'. If PLP_L1_CHANGE_COUNTER field is set to the value '0', it means that no scheduled change is foreseen. For example, a value of '1' indicates that there will be a change in the next superframe. This counter will always start counting down from a minimum value of 2. At the first frame of the superframe indicated by
PLP_L1_CHANGE_COUNTER field, the T2 receiver should decode the P2 symbols and update the L1-post signalling.
10.4.2.4.5
PLPs with zero FEC blocks in a given Interleaving Frame
EN 302 755 [i.1] explains that PLPs might be allocated no FEC blocks at all in a given Interleaving Frame, and there is therefore no BBFRAME frame to carry the in-band L1 signalling. The receiver will already know that this is the case from the in-band L1 signalling in the previous frame. There are two options for the receiver:
• It could wait until the subsequent frame and decode the P2 which always carries the dynamic L1 signalling for all PLPs.
• If the PLP carries in-band signalling for other PLPs, the receiver could use this information from the previous frame to receive one of these PLPs instead. These PLPs might in return contain in-band signalling for the wanted PLP.
10.4.2.5 Power saving
Receivers may save power by switching off some of the circuitry while signals for the PLP of interest are not being transmitted. This is most likely to be applicable to Type-1 PLPs, since they only have one sub-slice per T2 frame, and furthermore this sub-slice generally appears near the beginning of the T2 frame, close to the P2 (containing the L1 signalling) and any common PLPs (generally containing L2 signalling). All the information required is therefore close together at the beginning of the frame and the receiver need not receive the rest of the frame.
The use of in-band signalling can increase the possibility for power saving, since for most of the time even the L1 signalling in P2 will not need to be decoded: the dynamic information will already be known from the in-band signalling in the previous Interleaving Frame and any changes in the configurable information will be announced in advance in the in-band signalling.
The scope for saving power is greater still for PLPs which skip T2 frames, i.e. for which Ijump > 1. The receiver may ignore the frames which do not contain data for the PLP being received. In this case, in-band signalling is not mandatory and the receiver may need to receive the P2 signals.
The considerations for synchronisation in a power-saving receiver would be more complicated since the receiver would not be tracking the signal during the power-down period.
10.4.2.6 FEFs
The receiver can detect the presence of FEF parts by looking for P1 symbols and by decoding the L1-post signalling (in the P2 symbols). In the initial scan the receiver will look for P1-symbols. If the first P1-symbol found is from a
T2-frame, P2 can be decoded normally. The receiver will also see from the P1 if FEFs are present by looking at the S2 field 2 "mixed" bit. If the first P1 symbol found belongs to a FEF part, the receiver can check S2 field 2 "mixed" bit and if it is set, then the receiver knows that there are also other (T2) frames in the multiplex and the receiver should continue looking for those. The use of P1, including in the "FEF loop" of the acquisition process is described in more detail in clause 10.2.2.
When a T2 P1 has been found, the L1-post signalling in P2 can be decoded and the position of the FEF parts in the superframe, as well as their duration, can be found. The receiver can then correctly skip the FEF parts.
The use of FEFs makes management of the receiver's de-jitter buffer more complicated, and the parameters affecting the configuration of FEFs should be chosen to ensure that, if a receiver obeys the TTO signalling (see annex C of [i.1]) and implements the model of buffer management defined in clause C.1.1 of [i.1], the receiver's de-jitter buffer and time de-interleaver memory will neither overflow nor underflow. See clause 8.8 for more information about managing the de-jitter buffer.
As the content of the FEF part is not known, receivers should be able to ignore totally the content of the FEF part except the P1-symbol. In order not to affect the reception of the T2 data signal, the receiver's automatic-gain control should be held constant for the duration of FEF part, so that it is not affected by any power variations during the FEF part. It is even possible that the FEF part is empty (see clause 6.1.7.3).
10.4.2.7 Auxiliary streams
Auxiliary streams are for future definition. A receiver may completely ignore them if they are present. However, a useful feature for a receiver chip would be the ability to output the complex cell values for a particular range of cell addresses, either on the main output or by reading a register. This could then be used by external hardware or software to implement future applications.
One application for Auxiliary Streams has been defined, as part of the Transmitter Signature standard [i.22]. This application is intended primarily for professional applications, but could be used in the future for location-aware services.