AREA GANADERÍA – CABAÑA CAPRINA

Let inv(c, s) denote the inverter with the smallest power consumption that still achieves a slew of at most s at its output pin if its input slew is sopt and the load is

c.

Let t1_{:= inv(maxcap, sopt), and let t}2_{:= inv(cap}in_(t1_{), sopt). We compute d1 as}

in Section 4.1.4. Now we modify the repeater chain by adding a capacitance load of

capin(t1) in the middle of the first segment and consider it during the delay and slew

computation of the first stage. We then get the new delay d2 and set our branch

penalty to

dnode:= d2− d1

4.2 Blockage Map and Congestion Map

Placement blockages and wiring congestion information is given to the repeater tree routine via a blockage map and a congestion map, respectively. The blockage map is used to check whether a given point is blocked. The congestion map holds the global routing information showing on which parts of the chip routing space is sparse.

4.2.1 Grid

Both the blockage map and the congestion map share the same grid. The grid partitions the chip area into tiles. The tiles are nodes of a grid graph.

The bounding box ca of the design area is given by [caminx, camaxx] × [caminy, camaxy].

Definition 3 (Grid). A grid is a pair (xlines, ylines) of cutlines xlines = {x₀, x₁, . . . , xm} and ylines = {y0, y1, . . . , yn} with x0 < x1 < . . . < xm and y0 < x1 <

. . . < xm and m > 1 and n > 1. We call a grid feasible for a chip area ca if

x₀≤ caminx, camaxx < xm, y0 ≤ caminy, and camaxy < ym.

Most of the time, we use a grid with equidistant cutlines. An equidistant grid is accurate enough in the context of repeater tree insertion if it is not spaced too wide. Sometimes, however, one wants to use a Hanan grid given by the coordinates of all edges of significantly large blockages such that their positions are exactly captured in the blockage map.

Definition 4 (Tile). Given a grid (xlines, ylines) with xlines = {x₀, x₁, . . . , xm}

and ylines = {y0, y₁, . . . , yn}, we call the rectangle [xi, xi+1) × [yj, yj+1) for 0 ≤ i <

m and 0 ≤ j < n the tile(i, j) of the grid.

For a given point of the chip area, there is exactly one tile in a feasible grid that contains the point.

4.2.2 Blockage Map

The set of blocked regions for a repeater tree instance is stored in a data structure that we call blockage map.

The most important operation that is performed on the blockage map is searching for the nearest free location. Given a point in the plane, the blockage map is able to give us the nearest free location in a given direction rectilinear to the grid or the nearest free location in the whole plane with respect to `1-metric. Points on

blockage boundaries that are next to free points are considered as free.

4.2.3 Blockage Grid

For an existing blockage map and a grid, we also construct a blockage grid. The blockage grid stores information whether a grid tile is blocked or not:

Definition 5 (Blockage Grid). Given a grid (xlines, ylines) with

xlines= {x₀, x₁, . . . , xm} and ylines = {y0, y1, . . . , yn}

and a blockage map, a blockage grid is a function

bg: {0, . . . , m − 1} × {0, . . . , n − 1} → {0, 1}

where bg(x, y) = 1 iff tile(x, y) is completely blocked by the blockages of the map.

Shortest Path Searches

Typically, blockages do not block all wiring layers in a design. It is possible to cross them on higher layers. Repeater trees are also allowed to jump over blockages. However, the possible distance is limited by the slew and capacitance limits as it is not possible to place repeaters on blockages. Larger distances between repeaters caused by jumping over blockages also cost additional delay compared to an optimally spaced repeater chain.

At one step in our topology generation algorithm, we search for delay minimal paths between points in the design. We use a modified version of Dijkstra’s shortest path algorithm on the blockage grid for this task.

Given two points, we first identify the tiles they belong to in the blockage grid and then compute a shortest path between both tiles. The costs of an edge between two neighboring tiles depends on whether the tiles are blocked or not. Crossing unblocked space costs proportional to dwire. Costs over blocked area increase first

linearly and after a threshold quadratically with the distance the path already went over blockages.

4.2 Blockage Map and Congestion Map

4.2.4 Congestion Map

We implemented a rough global routing engine as congestion map. In contrast to a full-fledged global router, the congestion map does not try to find a congestion free global routing solution by all means. Instead, we embed a short `1-tree allowing

only small detours. We also limit the number of iterations spent for improving the routing. The advantage is that we still see congestion that we then can try to avoid during repeater tree generation. As can be seen in Table 7.2, using a full global router would increase the running time of our algorithm significantly. Our algorithm has recently been integrated into BonnRouteGlobal as a fast mode.

5 Topology Generation

The first step in our repeater tree algorithm is the construction of a repeater topology. A repeater topology specifies the abstract geometric structure of the repeater tree. Given an instance of the Repeater Tree Problem with root r and sink set S, we can define:

Definition 6. A topology T = (V (T ), E(T )) with V (T ) = {r} ˙∪ S ˙∪ I is an arborescence rooted at r with an embedding P l : V (T ) → R2 _{of the nodes into}

the plane such that r has exactly one child, the internal nodes I have one or two children each, and the sinks S are the leaves.

r

a b

− +

+

Figure 5.1:A topology for one root and three sinks. Steiner points like a and b are used to

route the topology around obstacles. Although we do not use directed edges in our figures, the edges in a topology are always directed away from the root.

We often call the set I of internal points Steiner points. Internal points with only a single child are used to force the topology to pass a certain point in the plane. Figure 5.1 shows an example topology. We should clearly note that the internal nodes do not represent repeaters and that the topology does not specify details about the exact placement, routing, and types of repeaters used in the final tree.

The length of a topology is

X

(v,w)∈E(T )

||P l(v) − P l(w)||.

We have seen that after repeater insertion delays in a repeater tree are roughly linear in the length of the segments. Connecting a sink to the root via a long path results in a higher delay to a sink. The required arrival times at a sink then decide whether a path is fine or too long. Consider the example in Figure 5.2. Both topologies have the same length, but, for example, the distance to the root is 8 for the upper right sink in the first case and 2 in the second one. This example

r + + + + + + + + r + + + + + + + +

Figure 5.2: Two topologies with the same shortest possible length but different timing

behaviour. While all sinks are reached within 4 segments on the right side, it takes up to 8 segments to the furthest sink on the left side.

illustrates that topologies have a high influence on the timing of a repeater tree. It is therefore crucial to build timing-aware repeater trees.

Topologies for a root and a set of sinks that consider timing information do not only have an application in repeater tree construction. They can also prove to be useful in global routing. A global router internally often has to compute Steiner trees for the nets of a design. The routing result can be better with regard to timing if the Steiner trees are timing-aware topologies.

In this chapter, we first develop a way to estimate the timing of a topology and then state the Repeater Tree Topology Problem. We show how our algorithm solves the problem and prove some theoretical properties for restricted versions of our algorithm.

The results in this chapter are joint work with Stephan Held, Jens Maßberg, Dieter Rautenbach and Jens Vygen (Bartoschek et al., 2007a, 2010).