A novel hybrid algorithm developed for underwater active sonar echolocation system has been proposed, implemented and tested based on an FPGA technique on a Xilinx University Program Virtex-II Pro Development System. The test results clearly state that the proposed system is capable of extracting exact target location and velocity information under reverberation-limited and shallow-water environment.
A review of the aims of the project, given at the end of Chapter I, shows a positive view on the acheivements. In fact, not only are all the original goals satisfactionary reached, some additional possibilities were also investigated during the implementation of the proposed system.
cross-correlation techniques for underwater sonar echo detection is propsed in a theortical platform, simulated and verified in Matlab, and then implemented on a commonly used FPGA hardware platform. The details of each stage of implementation are descirbed in previous chapters.
As put forward from the aims of the project, simulation results in Matlab and test results feeding back from the hardware platform all indicate this proposed system can exactly extract the target location and velocity information under severe noisy underwater conditions. The ANFIS succesfully removes the majority of noise and significantly increases the SNR. The noises left did not affect the efficiency of target extraction by wavelet transform. The requirement of resolution of target information on location and velocity was then easily satisfied.
Furthermore, the combination of a continuous wavelet transform and local optimum search algorithm kept the resolution advantage of the CWT and signicantly reduces the traditonal heavy computation time and resource requirements. This novel implementation of CWT is able to reduce by around 8 to 10 times the computation load compared to the conventional design.
In the meanwhile, besides the original project specifications, multiple target detection has also been investigated. Once target information is extracted, the target signal will be removed from received echo signals and the TME function block will process the rest of the signal again to examine whether there is another target signal buried in it. If another target is found, then the target information will be stored and this target signal will also
be removed before executing the TME on rest of the signal to check for other target information. These iterations will go on and on until all wavelet coefficients of the rest of the signals are below the threshold, which is defined according to the amplitude of the wavelet coefficients of pure noise.
The implementation of the ANFIS on the hardware system is also an exploration of a new area. The ANFIS is very effective for dealing with the chaotic nature of impulse noise; however, the heavy computation load limits its use in practical applications. In this proposed design, the ANFIS system is implemented using the embedded RISC core in the FPGA chip. 2 inputs and 4 membership functions are adopted in the design. The ANFIS function is written in the C-language, compiled by XILINX EDK 10.1 and stored in instruction rams for the embedded RISC cores. Once the hardware system is processing the input signals, these instructions will direct embedded RISC cores to operate the arithmetic operations needed for the ANFIS and feed back the results to the hardware system. In this way, the translation time for the ANFIS hardware implementation from a high-level language to a hardware language is reduced by the compiler of the XILINX EDK 10.1. Since the embedded RISC cores take most of the ANFIS computations, it will not consume the ordinary FPGA resources. Therefore, the hardware consumption is reduced. Following this method, if the technique of embedded DSP core develops to a certain scale, a real time implementation of the ANFIS on a FPGA would be feasible.
underwater active sonar echo location system presented in this project, demonstrated the following benefits:
The novel implementation of CWT by combining CWT with local optimum search algorithm significantly saves computation time for CWT and makes it more feasible to practical applications and real time applications.
The implementation of the ANFIS on an FPGA board indicates in the future a real-time ANFIS operation VLSI implementation would be possible.
The hybrid system explore the possibility of using ANFIS and CWT in practical applications and the test results supports the capability of the hybrid system and it is a new way to adopt computation-consuming algorithms such as ANFIS and CWT in practical applications.
The test for multiple target detection shows the proposed system is not only be able to capture the information of a single target, it can also detect multiple targets under severe noisy system precisely.
The implementation on a commonly used hardware system indicates the cost of this proposed system is affordable for most institutions. Therefore resource cost would not be a limit to turn this proposed system into real applications.
The test results show with limited hardware resources, the proposed hybrid sonar system is still able to produce satisfactory target information.