M odelling of MESFETs is a complex issue and detailed accounts can be found in the literature [72-77]. In a practical situation these sophisticated m odels often have little relevance, as the circuit designer is often restricted to the m odels w hich can be used w ith a circuit sim ulator w ith pre-set m odels. For the sim ulation carried out for this project, the SPICE circuit sim ulator w as used w hich provides tw o m odels suitable for MESFET sim u la tio n .
The sim plest m odel is the Shichm an-Hodges m odel [78], w hich was
developed in 1968 for the sim ulation of insulated gate field effect transistor (FETs). This m odel separates the FET operation into three regions - cut off
defined by equation (4.3.2.1), the triode region (sometimes referred to as the linear region) defined by equation (4.3.2.2) and the saturated region w hich assum es quadratic FET behaviour defined by equation (4.3.2.3).
Id = 0 cut-off (Vg,<Vto) (43.2.1)
Id = ) S [ 2 ( - Vto)V^ - VJ, ](1 + AV,, ) triode region (4.3.2.2)
Id = ~ (l + AVjJ saturated region (4.3.2.3)
(v^>V^-Vto)
W here Id = drain current, Vgg = gate-source voltage, = drain-source voltage, Vto = threshold voltage, p = device gain A /V ^ and A, = 1 / (early voltage) 1/V . The Id vs V^g FET characteristics governed by the Shichman- H odges m odel is show n by Fig 4.3.2-1
Saturation Region Linear Region ^fy Vds=Vgs-Vt( Bou 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Drain-Source Voltage (V)
Fig 4.3.2-1 Shichman-Hodges Model of FET Characteristics (P= lmA/V2,X = 0.1V-l,Vto = -2V)
This m odel is useful d u e to its simplicity, b u t w hen com pared to the m easured MESFET data it is often found to be inaccurate, the most
pronounced dep artu re occurring betw een the transition of the triode region to the saturated region. A n effect com m only observed in GaAs MESFET is that the knee' of the Id-Vjg curve appears at a low er V^g than predicted by the Shichman-Hodges (S-H) m odel and the onset of saturation occurs at a constant V^g rather th an along a quadratic curve indicated by the boundary line in Fig 4.3.2-1. This effect is caused by electron velocity saturation and is know n as the early saturation effect [79]. In Fig 4.2-1, electron velocity is show n to reach a high-field m axim um value w hen an electric field of approxim ately IV /jim is applied, thus increasing the field further will not increase the current flow.
A m ore sophisticated m odel which can also be used w ith SPICE is the Curtice m odel [80]. This replaces the Shichm an-H odges equations w ith a single expression adding a hyperbolic tangent to adjust the saturation point
show n by equation (43.2.4)
Id = p { v ^ - V to )'(l + ^V ^)tanh(aV ^ )
W here a is a device constant.
(4.3.2.4)
An u n u su al characteristic of the GEC-Marconi, low threshold MESFETs is the absence of any significant early saturation. Since circuit designers have chosen to exploit the early saturation effect in GaAs [81] which has been successful in some circumstances, the data provided by Bradford University and supported by the literature indicates that it can not be used as a general circuit design m ethod [82]. In particular devices w ith a low Vto such as these, generally saturate at V^g = Vgg - Vto [82]. This can be best illustrated by Fig 4.S.2-2, w hich show s the Id vs V^g of the m easured data for a 20pm GaAs MESFET along w ith a best fit Shichm an-Hodges and Curtice models.
solid line = measured GaAs MESFET line = Curtice
— line = Shichman - Hodges
< E Vgs=T).2v g t U à V gs=-0.4v 0.6 0.4 0.2 0 0.5 1.5 2 2.5 3 Drain-Source Voltage (V)
Fig 4.3.2-2 M easured Characteristic of the GEC-Marconi 20pm GaAs MESFET w ith Shichman-Hodges and Curtice m odels
The sim ilarity betw een the m easured data and the Curtice m odel is clearly show n to be the closest at low values of Vgg (ie close to Id = Idss), w hile accuracy is reduced as the GaAs MESFET approaches the threshold voltage. In addition, if the MESFETs are operating in saturation only, this enables the use of the Shichm an-H odges m odel, since in the saturated region of
operation the Shichm an-Hodges and the Curtice m odel converge.
For this reason the circuit design is restricted to operate well into the saturated region, w ith V^g = 2.5V w here the MESFET behaviour is m ore predictable and allows the use of a public dom ain sim ulator such as SPICE.
4.3.3 MESFET Geom etry
For the realisation of an integrated continuous tim e filter, small size and low pow er dissipation are im portant considerations. As such, the sm aller the MESFET devices available for the circuit design, the lower the pow er consum ption of the filter. A lthough m odelling data w as provided for
MESFET geom etry up to 300|im, the m inim um size device is considered the m ore prom ising candidate for use.
The MESFET m odelling param eters for the 20|im and 40|im gate w idths w ere supplied for a single wafer and betw een separate foundry runs. The results are show n on Tables 4.3.3-la & b.
D evice Size P Vto X oc
20|J.m 26% 11% 19% 16%
40|xm 13% 11% 63% 28%
Table 4.3.3-la M aximum Variation of MESFET Param eters Across a Single Wafer
D evice Size P Vto X a
20|im 26% 15% 54% 24%
40pm 16% 17% 67% 32%
Table 4.3.3-lb M aximum Variation of MESFET Param eters Across Four Foundry Runs
It is clear from this data th at the MESFET characteristics can show significant variation across a single w afer and an even larger variation betw een
separate foundry runs. Data w as also provided for devices w ith gate w idths of up to 300|im and these all show a sim ilar range of variation.
As a result of these large param eter variations it is clear th at to ensure
device characteristic scaling in proportion to the device size is impractical. If a variety of device geom etry were used in the circuit design, w hich is often the case [83], particularly so in CMOS, the param eter variation m ay cause non-optim um DC operating conditions. Thus, in addition to the use of the Shichm an-Hodges m odel, a further restriction is to use a single geom etry device throughout the design. As such, the m inim um size MESFET w as chosen.
From the data provided, a Shichm an-H odges m odel [78] for a 20pm MESFET device w as determ ined w ith high - low param eter values, based on m eaured tolerances, show n by Fig 4.3.3-1.
<
E
solid = measured GaAs MESFET •— line = high parameter value
line = low parameter value
g u
I
0.8 0.6 0.4 - 0.2 0.5 2.5 Vds (V)Fig 4.3.3-1 Simulated Id - V^g Characteristics for a 20|im MESFET (Model Param eters derived from M easured Data)
In m ust be stressed how ever, that the param eter variation observed m ay be attributed to the developm ent of this experim ental low threshold process and as such, comm ercially available GaAs MESFET devices m ay not exhibit such a w ide variation.
4.3.4 The AC Sm all Signal M odel
Once the DC operating conditions and device geom etry are fixed, the sm all signal model for the 20)im MESFET is sim plified. As is the case of the DC m odel restriction im posed as a result of using the SPICE sim ulator, only the predom inant AC param eters are chosen to represent the small signal
operation of the device.
W hen analysing MESFET (or any FET) circuit it is useful to define the
transconductance, gm and the output conductance, go. These param eters are derived from the satu rated region equation (4.3.2.3) of the Shichman-
H odges m odel and can be defined as:
Sm = -2 /î(V ,-V lo )(H -W ,) (43.4.1)
go =
V ^ d s/v
= Aj3(V^-Vtof (43.4.2)
As show n by equations (43.4-2) and (4.3.4-2), both the value of g ^ and g^ are determ ined by the DC operating conditions, V^g and Vgg, therefore at a given operating point a sm all signal description of the MESFET is given by equation (4.S.4.3).
id = gmVgs+ goVds (4.3.4.3)
Due to the DC m odelling restriction discussed in section 4.3.2, the MESFET w as chosen to operate well into saturation w ith V^g = 2V5, thus to
accom m odate g ^ tuning, Vgg m ust be varied. How ever, the use of active loads in GaAs MESFET technology is w idespread and is often achieved by the use of a single MESFET current load [84,85], w ith Vgg set to zero. If g ^ tuning w as im plem ented by varying Vgg, resulting in varying DC bias currents, large DC voltage offsets w ould occur w ithin the circuit. This in tu rn w ould alter the DC condition im posed to m aintain the devices in saturation. Therefore a further restriction is im posed u p o n the circuit design, that all MESFET devices operate at Vgg = 0 that is. Id = Idss. In addition, an advantage of this restriction is show n by Fig 4.3.2-3 that the Shichm an-H odges m odel is the closest m atch to the m easured MESFET data at Vgg = 0. D ue to the severe design restrictions, g ^ tuning can only be
achieved by breaking the design requirem ents, by biasing the MESFETs in the triode region to act as variable resistors.
As a result of the m axim um variation of MESFET param eters show n by Fig 4.3.3-1, the corresponding variation in g ^ w ould also be large. For the
d ep en d an t upon the OTA-C integrator Gm/CL- A lthough Gm is required to vary as a result of the tolerance of the fabricated load capacitance C^, the m axim um u p p er centre frequency w ould depend u p o n the MESFET device gjj^, since this value w ould be reduced for tuning. As such, to ensure that a m inim um centre frequency of 60MHz (Chapter 3, section 3.4) is obtained, the low er limits of the sim ulated GaAs MESFET param eters w ere chosen for the circuit design.
A n u n u su al property of the GEC-Marconi, low threshold MESFET is th at the o u tp u t conductance, g^ of the devices is significant. The intrinsic gain, g ^ /g o show n by equation (4.3.4-4), derived from equations (4.3.4.1 &2) is dependant u p o n the reciprocal of the early voltage, A and the bias conditions of the MESFET.
Sjs- = (43.4.4)
go A (v ^ -V to )
As, illustrated by Fig 4.3.3.1, the Id vs V^g curves are alm ost level in the saturated region, indicating a early voltage of 12.5V (ie X of O.OSV"^). If the low er limits of the sim ulated GaAs MESFET param eters of Fig 4.3.3-1 are used, a gain g ^ / g^ of only 30 is determ ined under the operating conditions of V^g = 2.5V and Vgg = 0.
H ow ever, the Id vs V^g characteristics of Fig 4.3.3-1 w ere obtained from DC m easurem ents of the GaAs MESFET w hich m asks a p ro p erty w hich has a serious consequence for circuit design, the frequency dépendance of the o u tp u t conductance, g^. This frequency dépendance of drain conductance is caused by the trapping and subsequent therm al re-em ission of electrons in the substrate [86]. This therm al process is slow, having a tim e constant of the o rder of Im S to lOOmS. As a result of this effect, X m ust be changed for DC and AC analysis of the circuit. For the experim ental low threshold devices to be used, detailed AC (ie Scattering-param eter) inform ation w as not
available, thus the foundry guide [66] indicated that the AC MESFET gain, gm /go is typically in the range of 8 to 15. If a m id value of 11.5 is chosen to
represent the MESFET AC gain, this w ould correspond to an AC X of 0.3V"^. The consequence of this is that the DC o u tp u t conductance, go w ould be 96|iS, w hile for frequencies above IK H z the o u tp u t conductance w ould increase to 360pS.
A m ajor factor in determ ining the speed of a sem iconductor device is the parasitic capacitance. The charge depletion region of a sem iconductor device form s this parasitic capacitance. The depletion region beneath the gate
produces parasitic capacitance betw een the gate and source, Cgg and the gate and drain, As the w idth of the depletion region is determ ined by the applied voltage, each capacitance m ay be considered as a Schottky-barrier device w ith a voltage dependent capacitance. In norm al operation the MESFET is biased w ith > Vgg, im posed by the design operating
conditions th at V^g = 2.5V w ith Vgg = OV. U nder these conditions, Cgg » Cg^ and w ill dom inate the in p u t capacitance of the MESFET. The variation of C gel w ith respect to applied voltage can be approxim ated by the expression derived for the ideal m etal-sem iconductor junction [87] and given by equation (4.3.4.5).
f t
W here Cg^^^ = zero volt capacitance, Vg^ = source-drain voltage and V^^^ = built-in voltage for GaAs at 0.8V.
This equation is useful in m any circumstances, b u t does n o t correctly describe the value of capacitance beyond the threshold voltage Vto, giving infinite or com plex values for voltages equal to, or larger than V|^-. For junction voltages equal to or beyond the threshold voltage, the depletion layer extends to the substrate and the associated capacitance w ould fall to zero, w ith only fringing capacitance rem aining. H ow ever, w ith the self im posed design restrictions of operating the MESFET u n d er a comm on bias condition w ell into the saturated region, the value of parasitic governed by
equation (4.3.4.5) is only used as a first order approxim ation to determ ine the ft.
Since no AC inform ation for the 20pm MESFET w as available, an estim ated value for the parasitic capacitance can be found by know ing th at the process is intended to have a m inim um f t of 20GHz. In addition, since the device is sym m etrical the assum ption that Cgg^ = can be m ade. Thus the
operating capacitance Cgg and Cg^ can be found using the expression fo r/t:
8>i
2 ^ C ^ + 0.49C,,„) (4.3.4.6)
By using the Shichman-Hodges equations, (4.3.4.1) and (4.3.4.2), an AC X of 0.3V“^ and the m etal-sem iconductor junction equation (4.3.4.5) in
conjunction w ith the f t equation (4.3.4.6) a sm all signal m odel for the 20pm GaAs MESFET device is derived and show n by g Fig 4.3.4.-1 w ith SPICE
param eters for a JFET Level 1 M odel given in Table 4.3.4-1.
drain gate
source
Parameter Value Vto -l.OV P 1.2mAA^ X 0.3V ‘ » PB 0.8V Cgso 22fF Cgdo 22fF r - 1 * DC value 0.08V'
Table 4.3.4-1 SPICE Parameters for the 20|Lim GaAs MESFET
A small signal frequency response is show n by Figs 4.3.4-2a & b indicating MESFET gain gm/go f t using the JFET Level 1 M odel above operating at the DC conditions of V^g = 2.5V and Idss.
<N I
-10
1 0"
Freq (Hz)
Fig 4.3.4-2a Simulated Small Signal Frequency Response of 20pm MESFET C urrent Gain H21 £ Freq (Hz) 12 10 8 6 4 2 10"
Fig 4.3.4-2b Simulated Small Signal Frequency Response of 20pm MESFET Voltage Gain (gm/go)
4.4 C onclusions
In this chapter the GaAs MESFET characteristics of m easured devices have been com pared to device m odels used for circuit sim ulation. In general the m ore complex the m odel the greater the accuracy to w hich the m easured data is characterised. In addition the m ore complex the device m odel the m ore sophisticated the sim ulator required to su p p o rt the model.
An approach is to use the sim plest GaAs MESFET m odel available (Shichman-Hodges) and to bias the device at the p o in t w here the m odel provides the greatest accuracy. This w ould allow the use of a public dom ain sim ulator such as SPICE w hich supported the use of the Shichm an-Hodges m odel.
Therefore, as a result of the restrictions of the sim ulation tool used, the observed variation of the device characteristics from the Shichm an-H odges m odel to the m easured data and the variation of data w ith various
geometries m easured, the circuit design was restricted to the use of a GaAs MESFET biased in deep saturation, operating at id=idss and the use of a single geom etry device throughout.
This will present a very dem anding challenge to the design of a fully tunable 2nd order bandpass filter realised in GaAs MESFET technology.