In PWM the width of a constant amplitude pulse carrier within an isochronous frame is modulated in sympathy with the modulating signal. Leading, trailing or double edge modulated PWM may be generated by comparison of the input signal with a linear ramp waveform, triangular in the case of double-edge-modulation. Leading or trailing edge modulated PWM may be generated by comparison of the modulating signal with a constant amplitude linear ramp waveform, see Fig. 2.6. The frequency of the ramp signal is constant and must be equal to or greater than twice the modulating signal frequency [Suh]. PWM may again be divided into two categories depending on the sampling form: naturally sampled PWM (NSPWM) or uniformly sampled PWM (USPWM). In the former case, comparison is directly carried out at the comparator, whereas in the latter case the level shifted modulating signal is routed first through a sample and hold circuit where samples are equally spaced in time irrespective of the input signal amplitude, see Fig. 2.6. The comparator gives a logic high output as long as the ramp waveform stays below the level shifted modulating signal.
The trailing edge modulated naturally sampled PWM pulse train may be expressed as
[Wilson93>],
«si n( w<ycr) * J k(nmnw)
sincomt + 2 , i > — *--- -sin in c o j- n n )
% nn % nn 00 ±c0 J.(nmn I (2-1) Z i ktii nn 1 1 W 1 = - + — 2 2
where mw is the PWM modulation index (0 < mw< 1), com and coc are the modulating signal and carrier angular frequencies, respectively. Jk{x) is the Bessel function of the first kind, order k.
The second term of Eqn..2.1 shows the base band component, whereas the combination of the third and fourth components produces the carrier frequency and its harmonics. The double summation represents the characteristic PTM series of diminishing side tones set around the carrier frequency and all its harmonics, see Fig. 2.7.
ciock ^ 4 4 4 4 4 4 Analogue input PWM in p u t. Edge detector S&H Input signal Ramp : Time USPWM
max. ■ unmodulated max. + deviation *_____4 i *deviation Modulation t Tel2 (a) S&H PWM output Clock DC shift Ramp Comparator (b) s&H ' "A.. Signal output Ramp (c)
Fig. 2.6 PWM signal generation: (a) PWM waveforms, (b) modulator and (c) demodulator.
c
fm fc
Frequency
Fig. 2.7 Naturally sampled PWM spectrum.
In comparison, USPWM spectrum contains harmonics of the signal frequency in the baseband region [Wilson%%,9\]. Thus, at the receiver, conversion to PAM waveform is required before the filtering process, whereas demodulation of NSPWM is accomplished by threshold detection and simple low pass filtering. From the hardware point of view, NSPWM is preferred because of its simplicity. However, if the pulse duration is small compared to sampling period, then the difference between these two schemes is insignificant [Carlson]. The main advantage of USPWM is that it produces lower distortion and higher signal to noise ratios by virtue of the greater modulation index that may be used [Ghassemlooy94].
In both PWM schemes, the amplitudes of the side tones increases with the sampling ratio and the modulation index. The modulation index is defined as the maximum pulse width deviation to the unmodulated pulse width, when the unmodulated pulse width is half the sampling time, see Fig. 2.6, The modulation index, mw can be expressed as,
where tw is the maximum pulse width variation, see Fig. 2.6. The unmodulated pulse width is assumed to be 7c/2, where Tc = \!fc% The optical bandwidth requirements for USPWM is [Ghassemlooy91 /1 ],
USPWM 5„ = / m(3 + rnnj) + 2 fs (2.3)
and for NSPWM is,
(2.4)
where f m is the baseband frequency and f g is the guard band.
The SNR of the regenerated signal at the NSPWM optical receiver output is given by,
From Eqns. 2.5 and 2.6 it is evident that the performances of both the PWM schemes are modulation index dependant. Furthermore, from Eqns. 2.3 to 2.6, USPWM performance is also bandwidth as well as sampling ratio dependant. The main factor that determines the maximum modulation index is the linearity of the analogue ramp. For the transmission to be linear, the ramp waveforms employed at the transmitter and the receiver should be identical, since any nonlinearity here will cause harmonic distortions in the recovered signal [Berry]. This is not always achievable due to component tolerances and operating conditions. Ghassemlooy et al reported that for good linearity system should be operated below modulation index of 50 % when it gives 2nd harmonic distortion of -35 dB, for higher indices the harmonic distortion further increases accordingly [Ghassemlooy94]. However, this short coming can be avoided by adopting digital techniques for implementing PWM, thus the name digital pulse width modulation (DPWM) [Ghassemlooy93/3]. Here the pulse widths are defined in terms of
(2.5)
and for the USPWM system,
discrete time slots which are proportional to the instantaneous amplitude of the modulating signal. Figure 2.8 shows the system block diagram.
The modulator contains a M bit counter which counts from 0 to 2^-1 within the sampling period. Thus the counter clock frequency f w is determined by,
L = f c(2M+gJ) (2 J )
Where f c is the sampling frequency as in analogue PWM. A few additional time slots (gw) are included in each PWM frame to avoid pulse overlapping.
Modulating
signal Sample and hold Sample DPWM Reset Sampling clock Slot clock Counter Latch C o m p a ra to r ADC (a) Enable Clear DPWM Output signal Reset LPF DAC Counter Latch Timing control (b)
Fig. 2.8 DPWM system block diagram (a) modulator and (b) demodulator.
The counter is reset to zero at every sampling instant. The counter output is compared with the latched symbol corresponding to the present signal sample, i.e. the output from the ADC. When they are equal, the comparator output goes low generating the desired DPWM signal. At the demodulator a counter is employed which simply counts the number of clock cycles for which the DPWM input signal is active. The DAC generates a PAM signal from the recovered symbols, which is then sent through a low pass filter
to extract the transmitted signal. This scheme has been shown an exceptional linearity compared to analogue PWM and does not suffer from harmonic distortion at higher modulation indices. However, it suffers from quantisation error. Quantisation error can be minimised by choosing higher resolution ADC/DAC. Results presented by
Ghassemlooy shows that digital PWM outperforms analogue PWM by up to 6-10 dB
when operated at 50 % modulation index [Ghassemlloy93l3\