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HORARIO CLASES - GRAO

In document uía da acultade de atemáticas (página 138-144)

TX Off

AI part = 4,096 chips 1,024 chips 32 real-valued symbols

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8.7 The Paging Indicator Channel (PICH)

The PICH is used to provide a discontinuous reception function for paging on the UMTS air interface. Thus it carries a stream of paging indicators, each of which is associated with a group of UEs. A paging indicator set to ‘one’ indicates that there is a paging message for a UE in the group of UEs associated with that particular paging indicator. All the UEs in the group will then read the PCH channel within the SCCPCH associated with the PICH.

The structure of the PICH is shown in the diagram. It is based on the standard 10 ms radio frame but is divided into 300 bit periods, of which only the first 288 are used.

These 288 bits may be grouped to provide 18, 36, 72 or 144 paging indicators per radio frame.

Higher-layer signalling is used to indicate to the UE which paging indicator it is associated with and how frequently that paging indicator will occur. This is based on system parameters and on the UE’s International Mobile Subscriber Identity (IMSI).

144 2

72 4

36 8

18 16

No of paging indicators per radio frame Bits per paging indicator

288 Paging Indication Bits TX-Off 12 Bits

SF = 256

10 ms Radio Frame

b 0 b

1 b

2 b

287 b 288 b

289 b

... 299

Figure 25

The Paging Indicator Channel (PICH)

8.8 High Speed Downlink Packet Access (HSDPA) Channels

Higher-layer traffic that is to be carried using HSDPA is mapped from the logical channel DTCH to the transport channel HS-DSCH. This in turn will be mapped into a High Speed Physical Downlink Shared Channel (PDSCH). However, the HS-PDSCH does not operate as a standalone channel. In order for a UE to receive data using HSDPA resources it must already have an associated DPCH in operation.

Additionally, there are two other HSDPA channel types used at the physical layer to support the HS-PDSCH. All these channels are summarized in the diagram.

The HS-PDSCH carries higher-layer high-speed data in the downlink direction. There can be up to 15 HS-PDSCHs configured on a single cell. This channel operates with a fixed spreading factor and access to it is controlled with a fast scheduling process.

The High Speed Shared Control Channel (HS-SCCH) is a downlink channel that carries the fast scheduling information indicating the allocation of HS-PDSCH resources on a cell. There can be up to four HS-SCCHs configured on a cell.

The High Speed Dedicated Physical Control Channel (HS-DPCCH) is an uplink channel carrying feedback information and packet acknowledgements for UEs receiving on an HS-PDSCH. There will be one HS-DPCCH for every mobile using HSDPA resources on a cell, although the channel is only transmitted when required to acknowledge a block of received data.

DTCH

HS-DSCH

HS-DPCCH HS-PDSCH HS-SCCH

DCCH

DCH

Data RRC control

DPDCH DPCCH

HSDPA Logical

Transport

Physical

DPCH

Associated

Control Associated

Control

Figure 26 HSDPA Channels

8.9 HSDPA Channel Organization and Timing

HSDPA is based around the normal timeslot structure, but all the HSDPA-specific channels are grouped in 2 ms blocks of three slots providing a shorter radio frame.

A UE allocated HSDPA resources will be instructed to monitor the HS-SCCH.

Scheduling instructions are carried within each 2 ms three-slot block in the HS-SCCH. A scheduled 2 ms data block in one or more HS-DPSCHs for a UE has a two-slot offset from the HS-SCCH, as shown in the diagram. The UE will receive the indicated HS-PDSCHs and process the required data. Quality and acknowledgement information is then sent back to the Node B in the HS-DPCCH. The offset between the received data in the HS-PDSCH and the corresponding HS-DPCCH transmission is determined by higher-layer system parameters.

Depending on UE and Node B capability the HS-PDSCH may be transmitted using either the standard UMTS QPSK modulation scheme or the higher-level modulation scheme 16QAM. At the fixed spreading factor of 16 the respective physical layer bit rates for these two modulation schemes are 480 kbit/s and 960 kbit/s. Also depending on capability, the UE may be able to receive up to 5, 10 or 15 HS-PDSCHs simultaneously.

DL DPCH

HS-SCCH

HS-PDSCH (1–15)

HS-DPCCH

UL DPCH Uplink

Downlink

2 ms

2 ms ~7.5 slot offset (2 slot offset)

UMTS timeslots

Modulation Scheme

Fixed Spreading

Factor

Bits per Slot

Bits per HS-DSCH Sub-frame

Channel Bit Rate (kbit/s)

QPSK 16 320 960 480

16QAM 16 640 1920 960

Figure 27 HSDPA Structure

9.1 General DL Timing within a Cell

There are many different physical channel types defined for the UMTS air interface;

the timing for all these channel types is related to the slot and frame structure built on 10 ms blocks. However, within a cell there may be different offsets applicable to this timing structure when considering different physical channels on the cell.

The diagram is a summary of the timing relationships between the main DL channels.

9.1.1 DL Reference Timing on a Cell

The reference against which all other offsets are measured is the slot and frame structure of the SCH, CPICH and PCCPCH on a cell. As can be seen, all these physical channels are aligned. Thus acquisition of the slot and frame timing from the SCH and phase alignment from the CPICH provides alignment with the PCCPCH.

AICH access slots start at the same time as PCCPCH with System Frame Number (SFN) modulo 2 = 0.

9.1.2 DL Common Channel Timing on a Cell

The frame timing for any SCCPCH on a cell may be offset from the PCCPCH and offset from each other. There are 150 offset values available, which are multiples of 256 chips. Thus the offset of the kthSCCPCH is given by:

τ

SCCPCH,k= Tkx 256 chips where: Tk= 0,1,2 … 149

The PICH timing is

τ

PICH= 7680 chips before the corresponding SCCPCH.

9.1.3 DL Dedicated Channels on a Cell

The frame timing for any DPCHs on a cell may be offset from the PCCPCH and offset from each other. Within any given DPCH, the subchannels DPCCH and DPDCH are aligned. There are 150 offset values available, which are multiples of 256 chips. Thus the offset of the nthDPCH is given by:

τ

DPCH,n= Tnx 256 chips, where: Tn= 0,1,2 … 149 9 PHYSICAL CHANNEL TIME ALIGNMENTS

Any CPICH

P-CCPCH Radio frame with (SFN modulo 2) = 0

#0 #1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 #14 Radio frame with (SFN modulo 2) = 1 Primary SCH

Secondary SCH

kth SCCPCH

PICH for kth SCCPCH

AICH Access Slots

τ

SCCPCH,k

In document uía da acultade de atemáticas (página 138-144)