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The bottom membrane doesn’t have any pattern on the device layer side. However, the four insulating pillars that were to be used in assembly step to define the gap distance between two membranes need to be prepared while the bottom membrane is fabricated. After the gap pillars are placed in the DL of the bottom membrane, 2 mm x 2 mm square membrane is exposed in the middle of the chip by through wafer etch similarly to the X-shape trench in the top membrane fabrication. Individual process step is described.

Step 1: 25 µm thick silicon dioxide (SiO2) is deposited on the device layer (DL) and the handle wafer (HW) of the SOI wafer with CCP-Dep. Since the CCP-Dep can make deposition on only one side of the wafer, this deposition process is performed in two separate runs. The oxide deposition is done at 350⁰ C. As described in the design of the FPI filter, the necessary gap distance of the FPI filter is 25µm. This complicates the fabrication process significantly. The oxide on the device layer is to be the gap pillars after lithography and etch downstream. The oxide on the handle wafer is for the etch mask in the bulk micromachining. For this purpose, 6 µm of oxide thickness is enough. However, we found that asymmetric deposition of such a thick oxide only on one side of the wafer developed high surface stress that resulted in a curved wafer unsuitable for further process. In short, spin coater no longer maintains the vacuum between the wafer and the chuck necessary to spin it. To release the stress, we decided to deposit the same thickness of oxide on both sides.

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Step 2: An optical photolithography is performed on top of the 25 µm oxide layer deposited in the previous step to pattern the gap pillars on the device layer. Thick 7 µm photoresist is used to pattern an etch mask for the 25 µm oxide dry etch in step 3. Step 3: Four rectangular gap pillars are etched on 25 µm oxide layer deposited in step 1 in the AMTETCHER. With 350 nm/min nominal oxide etch rate, 75 minutes of etch time is necessary to fabricate the pillars. To prevent burnt PR during the Si dry- etch process, any remaining PR mask is removed with 20 min. of Piranha treatment. With these 3 steps, the gap pillar fabrication process on the DL of the bottom

membrane is completed. The back side of the wafer after steps 1-3 is shown in figure 5.12.

Fig. 5.12 The front side of bottom membrane wafer. Four gap pillars are patterned and etched on 25 µm oxide film. Also shown in the figure is the gold deposited on the pattern to accommodate eutectic wafer bonding attempt.

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Step 4: 1 µm PR layer is spin coated with SVGCOAT on the DL to protect the gap pillars and the polished surface while the bulk micromachining is performed on the HW of the bottom membrane. The reason we used the PR for this protective layer is that when we etch the BOX layer in 2% HF wet etch at the last step of the process, the oxide gap pillars have to be protected as well. This PR layer will be removed in 20 min. Piranha bath.

Step 5: An optical photolithography is performed on the 25 µm oxide layer deposited on the DW in step 1 to pattern 2 mm x 2 mm square well. This well exposes 25 µm DL from the backside of the SOI wafer and produces a thin membrane where the DBR mirror is deposited. Entire 400 µm Si in the handle wafer is through etched in the bulk micromachining. The PR pattern is used as an etch mask for the 25 µm oxide dry etch in step 6.

Step 6: The oxide mask for square well is etched on 25 µm oxide layer deposited in step 1 in the AMTETCHER. 75 minutes of etch time is used. The silicon under the oxide is to be etched out in the next step, and small amount of over-etch can be tolerated without any process complication.

Step 7: A 2 mm x 2 mm square well is etched on the HW of the SOI wafer. 400 µm thick silicon HW layer is removed with dry etch in the STSETCH. Though wafer etch for the square well takes 12 hr. and 30 min. To minimize the formation of the black silicon, and the etch rate changes due to increase in substrate temperature during the long etch, the trench etch is divided into three 4 hr. and 10 min. etch with

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30 min. cool down in between. The BOX as etch stopper no precise etch time control is necessary.

The back side of bottom membrane wafer after steps 1-7 is shown in figure 5.13.

Fig. 5.13 The back side of bottom membrane wafer. 2 mm x 2 mm square wells are patterned and etched through the handle wafer exposing 25 µm DL membrane.

Step 8: The fabrication of bottom membrane with the gap pillars is completed by last step to remove the BOX layer and the protective PR film. 2 µm BOX layer is

removed in 2 min. 6:1 BOE deep, followed by the removal of 1 µm PR using 20 min. of Piranha bath.

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Fig. 5.14 The Fabrication Process Flow of the Bottom Membrane

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