Impacts on climate change and fossil depletion

0 0.02 0.04 0.06 0.08 0.1 0.12

-150 -100 -50 0

|H| (dB)

CIC (N=5,R=28) sin compensation²

0 0.02 0.04 0.06 0.08 0.1 0.12

0

∠(rad)

f/f_s p

-p

(CIC+sin ) compensation² IIR 6 -order^th

(a) Gain and phase plot of CIC and IIR filters

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 -10

-5 0 5 10

|H| (dB)

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0

∠(rad)

f/fs

p

-p

CIC (N=5,R=28) sin compensation² (CIC+sin ) compensation² IIR 6 -order^th

(b) Zoom around the corner frequency of the designed filters

Figure 4.20: Theoretical performance comparison of IIR and CIC filters

4.3 Implementation

Details of the test bench are listed in Appendix A.1. The above selected filter structures were implemented on a Xilinx Virtex-2P-XC2VP30 FPGA. The logic development of these algorithms is carried out with the Xilinx System-Generator toolbox.

4.3.1 CIC with second-order sine compensation

The cascade of CIC filters with the compensation structure is represented in block schematic in Fig. 4.21. The used parameters of the CIC filter are the same as above (N=5, R=28 and M=1). The transfer function of the CIC filter has been evaluated from

(4.9) with the above selected parameters. Firstly the compensation part, which is only the 1^st Fourier component of exact compensation as shown in Fig. 4.13, is discussed. The expected magnitude response of the compensation can be written as in (4.12). In (4.12),

∆cos(ωR) represents the 1^st Fourier component of the ideal half-band compensation with the reducing gain of ∆, to ensure no pass-band overshoot. Further it can be written as second-order sine function as seen in (4.12), hence in [DM2008] [DH2009] it is referred as second-order sine compensation. The equation (4.12) can further be simplified to (4.13).

|Hc(jω)| = 1 + ∆ [1 − cos(ωR)] = 1 + 2∆



sin²ωR 2



(4.12)

|Hc(jω)| = 1 + ∆ [1 − cos(ωR)] = 1 + ∆



1 −1 2

e^jωR+ e^−jωR

= −∆

2e^jωR+ (1 + ∆) − ∆ 2e^−jωR

(4.13)

From (4.13), it is very easy to write the transfer function in z-domain as in (4.14). The equation shows it is very simple to realize this compensation.

Hc(z) = −∆

2 + (1 + ∆)z^−R −∆

2z^−2R (4.14)

The screen shot output of the CIC filter structure realized on a FPGA is shown in Fig.

4.22. There is no specific reduction of data rate at the input of differentiator blocks. The implementation of compensation part is shown in Fig. 4.23. The space characterization of the CIC and compensation parts together is given in Table 4.3. The table reveals a small hardware space requirement for these filters. As they are very easy to design and realize too, they are very popular. Due to these advantages, many commercially available filter devices have CIC filters in the first stage followed by an FIR filter.

4.3.2 IIR filter

It is known that IIR filters can be represented in many different forms and realized in all these forms. Commonly known are the direct form shown in Fig. 4.19, transpose form, cascade form and the parallel form. Simplest among them to realize is the direct form.

For a chosen sixth-order filter implemented in the direct form and its corresponding space requirement is shown in Table 4.3. With this method of realization, the slice utilization of the FPGA is very poor, which is mainly due to high-bit-wide polynomials (ref. Table 4.2).

As the polynomials are constant values, only look-up-tables (LUT) of slices are utilized which means higher usage compared to flip-flops (FF) (ref. Table 4.3).

input output

−^∆₂ + (1 + ∆)z^−R− ^∆₂z^−2R

h1 R

1−z^−R 1−z^-1

iN

Figure 4.21: Cascaded CIC and compensation structure

4.3 Implementation 59

Figure 4.22: Implementation of CIC filter

- /2D

Figure 4.23: Implementation of second-order-sine compensation

In order to overcome this drawback one can explore different forms of Butterworth filters, e.g. a cascaded structure. In this form of realization, higher-order transfer functions are decomposed into multiple reduced-order functions in cascade. For any even filter order, the transfer function is decomposed into a multiple cascade of second-order filters and odd orders as a multiple cascade of second-order filters and a first-order filter. Small sampling time used for filter realization on the FPGA allows to approximate the process to an analog system, as the error introduced using a simple numerical integration method such as first-order forward Euler is negligible. Hence one can directly employ continuous-time design rules for the filters. However, due to this discrete integration, condition for the stability of the filter is that the poles of the transfer function must lay within the circle of

Table 4.3: Logic usage for filter realization (% of respective available resource on FPGA uti-lized) LUT: Look-Up-Table FF: Flip-Flop

Filter type Different approaches Slices LUT FF

CIC+Compensation - 858 1252 593

(6%) (4%) (2%)

IIR-Direct 2874 5154 290

IIR approach (20%) (18%) (1%)

IIR-Cascaded 535 773 344

approach (3%) (2%) (1%)

radius = _T¹

s centered at −Ts in the “s” plane. This implies, as the ratio between the filter sampling frequency to the corner frequency is very high, the performance of analog and discrete system will more or less be the same, as this ratio starts reducing it is necessary to investigate the stability and the performance details more carefully.

Design method: The approach employed here can be found in textbooks on filters [HL1979]. The transfer function of a sixth-order IIR filter and its cascaded form can be presented as in (4.15) where it is decomposed into a cascade of three second-order filters

H(s) = ω_c⁶

where ωc is the corner frequency of the sixth-order filter. The slowest among these three filters has to be used in the front of the structure to avoid overflow due to high overshoot.

Implementation of individual second-order filters can be understood very simply by con-sidering an R-L-C series circuit. The representation of the transfer function in a block schematic is shown in Fig. 4.24. The gains used before the integrators are the ratio of sample time Ts to time constant, which is automatically normalized. The values for these three parameters can be chosen as given in (4.16) for the first second-order filter in (4.15)

H1(s) =

For the given corner frequency ωc = 2π·100 kHz, the product of LC is fixed, thus it is necessary to assume one among these values to fix the other. By taking C =10 µF, values for L and R becomes 0.25 µH and 0.082 Ω, respectively. With 10 MHz of sampling fre-quency, i.e Ts= 0.1 µs, the corresponding gains in Fig 4.24 are ^T_τ1^s=0.0325 and ^T_τ2^s=0.1214.

These values are reasonably bigger and can therefore be represented with very small bit-wide. During implementation, only a bit-wide of 12 is utilized for these constants in all

x(t)

Figure 4.24: Simplified block schematic of second-order low-pass filter (τ1= _R^L, τ2= RC)