Información suministrada por los estudiantes

The standard and proposed crossbar structures depicted in Figure 5.10 and Figure 5.11 respectively; are simulated in LTSpice IV, using signal and parameters stated in Appendix 5-1. The simulations are carried with the purpose of testing the feasibility of the proposed structure to improve the memory crossbar performance, and its ability to mitigate energy loss due to leakage currents. The standard crossbar structure is used as a baseline for comparison, and the structures were tested for both reading and

Operation WE/𝑅𝐸 A0 A1 C DATA D0 D1 WL0 WL1 WL2 WL3 BL1 BL2 Sel Write 1 x x 0 0/1 VP0/VP1 VP0/VP1 1 0 1 0 1 0 Float 1 x x 1 0/1 VP0/VP1 VP0/VP1 0 1 0 1 0 1 Float Read 0 0 0 x x VRead Float 1 0 0 0 1 0 1 0 0 1 x x VRead Float 0 1 0 0 0 1 0 0 1 0 x x Float VRead 0 0 1 0 1 0 1 0 1 1 x x Float VRead 0 0 0 1 0 1 0

120 writing processes for both high resistive and low resistive states i.e. binary 0 and 1 respectively.

A. Energy consumption in the crossbar

The dissipated energy during programming pulse i.e. the energy dissipated in all memory cells (M0 ‒ M3) is the same in both structures, as seen in Figure 5.12 This is explained by the fact that the voltage applied to the grid during programming operation is the same regardless of the structure. While for the reading process; the proposed structure demonstrated superior performance as expected. With more than an order of magnitude improvement in consumed energy of reading a stored 0, and almost six times less energy when reading a stored 1. This was due to the elimination of leakage paths; which resulted in most of the applied current to pass through the targeted cell rather than untargeted ones.

Figure 5.12: Summary of simulation results of dissipated energy during reading and programming

B. Energy dissipation due to leakage currents

The simulation results seen in Figure 5.13 are of leaked energy during the programming and reading. The results of the energy dissipated in untargeted cells showed a great variation between the two structures as expected. The proposed structure showed two and six orders of magnitude less leaked energy during programming to 0 and 1 respectively. This is directly tied to the elimination of

Program 0 Program 1 Read 0 Read 1

10-14 10-12 10-10 10-8 En er gy ( J) Proposed Structure Standard Structure

121 leakage paths in this structure by utilizing separate Word lines for each memory cell. Moreover, the proposed structure demonstrated more that thirteen orders of magnitude less leakage energy during the reading process as noted from Figure 5.13. Furthermore, it was noted that the leakage of reading process in the novel structure is the least of all. This is due to the fact that in addition to eliminating leakage paths, reading voltage VRead is much smaller than programming voltage VP, along with

shorter reading delays in the novel structure.

Figure 5.13: Summary of simulation results of leaked energy during reading and programming.

C. Programming and reading delays & programmed Rcrystalline

The programming duration for both structures was set to a constant value in order to evaluate the effect of underlying structure on the programmed resistance state. However, the built in capability to program all cells sharing a Bit line in the novel structure, gave it a superior performance in terms of programming delay per cell as shown in Table 5.6. This particular improvement in programming time is an additional architectural advantage along with leakage elimination.

Furthermore, the reading delay was measured as the time for the output to fully swing to 0 or 1 from the moment the address lines and the read signal were propped. It was found that the proposed structure demonstrated almost three times less delay to read a stored 0. Also, it showed more than an order of magnitude less time to read a stored 1 as seen from simulation results outlined in Table 5.6. This is due to larger

Progarm 0 Program 1 Read 0 Read 1

10-30 10-20 10-10 100 Le a k a ge E ne rgy ( J ) Proposed Structure Standard Struture

122 current supplied to the comparator due to less leakage, resulting in a faster voltage swing.

Table 5.6: Delay and programmed level simulation results summary

Operation Novel Structure Standard Structure

Programming 0 Delay (s) 10 n/N* 10 n/cell Programming 1 Delay (s) 200 n/N* 200 n

Reading 0 Delay (s) 1.23μ 3.31 μ

Reading 1 Delay (s) 0.929 μ 1.41 μ

Programmed Rcrystalline (Ω) 16.3213K 30 K Programmed Ramorphous (Ω) 200 K 200 K *(N≈ No. of cells in a Bit line)

The last tested metric was the programmed state. It was found that when programming to high resistive state i.e. storing binary 0; both structures cells were fully programmed to 100% amorphous phase of 200KΩ. While when programming to low resistive state; the standard structure demonstrated higher programmed resistance compared to the novel structure as shown in Table 5.6. This is a direct result of leakage, since less energy is delivered to the targeted cell. This results in partially crystallized cells, and accordingly a higher programmed Rcrystalline. This particular

leakage effect in standard structure jeopardizes the reliability of memory operation, and furthermore limits multilevel operation.

5.4.2 AC sensing

During read process; leakage currents in PCM based crossbars cause unnecessary energy loss. Therefore, in this section we explore a leakage minimizing sensing method that was first suggested in [119]. The sensing scheme was targeted to minimize reliability issues in Memristors as leakage currents are sufficient to program Memristor cell. However, the AC reading technique in [119] is considered compatible for PCM operation after certain modifications. Even though it will serve to a different

123 purpose, i.e. energy saving rather than read disturbs avoidance. The AC reading circuit is designed and tested in PCM based crossbar memories in simulation environment. Then it was compared to the standard DC sensing method. The comparison was carried out in order to accurately evaluate the improvement offered by the AC reading technique.