In the problem we consider we assume that a tree is rooted at the source r ∈ Z, while the remaining terminals in Z are the sinks. Thus, the tree is actually a Steiner arborescence for Z rooted at the source. An electrical signal should propagate from the source to the sinks via the constructed tree. When constructing the tree, several conflicting objectives must be taken into account. In particular, the following two objectives need to be considered:
The total length of the tree should be minimized since this reduces area requirements, congestion and power consumption.
The signal delay from the source to the sinks should be minimized since this reduces the overall clock cycle time.
An optimal solution for the problem that only considers the first objective is a rectilinear Steiner minimum tree (RSMT). This problem has received significant attention in the literature (Hwang, Richards and Winter [1992], Kahng and Robins [1995], Zachariasen [2001a]), and RSMTs of any practical size can be computed quickly (Warme, Winter and Zachariasen [2000, 2001]). Minimizing total length has traditionally been the prime ob- jective since this objective is also reasonably good with respect to signal delay in practice. Furthermore, for most terminal sets (also called nets), signal delay is not important; these nets are not part of the critical signal path of the chip. However, for those nets that are part of the critical signal path, signal delay is obviously very important.
In the past, the problem of minimizing sink delay was mainly attacked by using geomet- rical approaches. The delay of a wire was assumed to be linear in its length. So-called shallow-light algorithms limit the delay by bounding the radius of the tree (Nastansky, Selkow and Stewart [1974], Cong et al. [1992], Khuller, Raghavachari and Young [1995], Naor and Schieber [1997]). A similar approach is due to Alpert et al. [1993] who present a tradeoff between Prim’s and Dijkstra’s algorithm. Cong, Leung and Zhou [1993] justify that a Manhattan Steiner arborescence has good approximating properties with respect to delay. For newer VLSI fabrication technologies interconnect delays are becoming in- creasingly dominating when compared to gate delays (Cong et al. [1997]), thus linear delay approximation is not sufficient anymore. Therefore, algorithms directly incorporate a bet- ter delay approximation function (Prasitjutrakul and Kubitz [1990], Boese, Kahng and Robins [1993], Hu, Hou and Sapatnekar [1999], Lin, Liu and Hwang [2001]). For a com- parison between several different performance-driven Steiner tree construction algorithms, we refer to Alpert et al. [2006]. Boese et al. [1995a] proved that minimizing the sum of weighted sink delays can be solved to optimality on the Hanan grid. This is not true for minimizing the maximum sink delay as shown by Boese et al. [1994]. For a good overview, see also Kahng and Robins [1995].
In this section we consider the problem of constructing RSMTs — which have minimum total length — that are as good as possible with respect to some signal delay objec- tive. Therefore, without sacrificing minimum total length, we try to improve signal delay (if possible), that is, consider signal delay as a secondary objective when constructing RSMTs. The proposed algorithms can therefore be used to improve all minimum-length interconnections on the chip. However, for some nets on the critical signal path, it may be necessary to sacrifice minimum total length using alternative methods (Boese et al. [1995b], Kahng and Robins [1995], Peyer [2000]). Alpert et al. [2006] show that commonly used algorithms constructing timing-driven Steiner trees add only at most 2 % – 4 % extra wire length while improving the signal delay from source to sinks. The construction of (al- ternative) rectilinear Steiner trees that are good with respect to routability was considered by Bozorgzadeh, Kastner and Sarrafzadeh [2001].
For a given tree T spanning Z, let PT(r, zi) be the path from the source r to a sink
let wi > 0 be a positive weight for sink zi. We mainly focus our study on the following
problem:
Rectilinear Steiner Tree Problem with Weighted Sum of Path Lengths Secondary Objective (RSTPWP)
Instance: • A terminal set Z in the plane; • a designated source r ∈ Z;
• weights wi> 0 for all sinks zi ∈ Z \ {r}.
Task: Construct an RSM Tr such that Pzi∈Z\{r}wi|rzi|T is minimized.
An optimal solution to RSTPWP is denoted by RSM Tr. See Figure 3.1 for an illustration.
r r
Figure 3.1: Two RSMTs for the same set of terminals (depicted in black circle). The RSMT on the right has better signal delay properties than the RSMT on the left. In fact, the RSMT on the right is an optimal solution to RSTPWP since all paths from the source r to the sinks are shortest rectilinear paths.
The objectives of RSTPWP are motivated by VLSI design where it is important to build trees not only as short as possible but also with good timing properties. A signal which is propagated from the source through a tree must fulfill specified timing constraints. These constraints can be approximately reflected by weights wi for all sinks zi ∈ Z \ {r}, where
critical sinks receive a higher weight than less critical sinks.
The advantage of the problem formulation of RSTPWP is that it is simple and does not use any timing parameter. However, the weights must be chosen carefully in order to appropriately express criticality of sinks. A commonly used delay approximation is due to Elmore [1948]. The Elmore delay model serves as a good estimation for computing the signal delay from the source to the sinks in a tree T . Given a source resistance Rd,
resistance Runit and capacitance Cunit per wire unit, and load capacitances ci for every
sink zi ∈ Z \ {r}, the Elmore delay delT(zi) of a sink zi is defined as
delT(zi) := RdCT,r+ X e=(u,v)∈E(PT(r,zi)) re ce 2 + CT,v ,
where re := Runit· |uv|T and ce := Cunit· |uv|T denote the resistance respectively the
capacitance of edge (u, v) and CT,v the downstream capacitance of the subtree of T rooted