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All components of the power core were assembled building the VSC. For the newly designed systems, it is necessary to make commissioning of all parts in order to prove their functionality. This section presents some of the measurements results which were obtained during the commissioning of the designed VSC. These results are helpful for further investigation in Chapter 4.

As it is explained in Subsection 1.4.4, the hardware design of the VSC influences the EMI behaviour of the AC drive. The RF part of the conducted noise generated by the VSC is influenced by the switching behaviour of power semiconductors and by the impedance of the whole converter (power core). The initial information about the switching process (rise and fall times, energy loss and etc.) can be found in the datasheets of the applied power switches [141, 142]. However, the switching behaviour is influenced by the gate drivers and by the stray parameters in the commutation path, i.e. the design of the VSC. Therefore, it is preferred to measure the switching behaviour of VSC during the commissioning in order to ensure the exact values of switching losses. The switching behaviour of designed VSC was measured using the inductive load switching (double pulse test) similar as in [100]. The inductive load was set to be equal to 3 mH that is close to the inductance of the typical induction machine. The considered inductor was applied to each phase of the studied VSC. The DC link voltage is equal to the nominal input voltage of the studied system (540 V). The test were conducted under the output current of 9 A that is equal to the average value of the drain current at the maximum load. One power switch conducts only one half-wave of the output sinusoidal current [27].

According to (1.19), it is required to measure the drain current I_d and drain-source voltage U_ds to estimate the value of energy loss during one switching event. These parameters were measured using the differential probe and Rogowski coils (see Appendix D) for the voltage and current respectively. The resulting graphs are shown in Figure 3.6. It can be seen, that the measured switching behaviour differs slightly from theoretical curves in Figure 1.24b. The voltage U_ds starts to increase during the turn-off in Figure 3.6a as it is expected (see Figure 1.24b). However, the drain currentI_d decreases at the same time. This effect is caused by the external Schottky free-wheeling diodes which are not considered in Figure 1.24. If the external diodes are applied, the part of the I_d moves in the external diode to charge the anode-cathode capacitance. As it is explained in Subsection 1.4.4, the duration of voltage rise time is defined by the output current and by the value ofC_ds. Due to the relatively small value of the output current, the voltage overshoot is not observed in the measurements. However, some ringing is presented inUdssimilar to the measurements results which were obtained in [100].

The measured turn-on process, which is presented in Figure 3.6b, corresponds to the theoretical be- haviour in Figure 1.24. The only difference is that the turn-on process in Figure 1.24 was considered for the low side switchS₂. The drain-source voltage on low side switchS₂is equal toU_{dc− Uds}. The turn-on process in Figure 3.6b starts with a current rise. After the drain current I_d reaches the value of output current (9 A), the drain-source voltage starts to fall. Despite, that the Schottky free-wheeling diodes with almost zero reverse recovery were applied, current overshoot can be observed due to the discharge of C_ds. This corresponds also to the results obtained in [99, 100].

Due to the presence of stray inductance in the commutation path, a small value of the voltage decrease ∆U = 52 V can be observed during the current rise in Figure 3.6b. By measuring the rise time of the drain

0 50 100 150 200 0 200 400 600 Time,ns Uds ,V 0 10 20 30 Id ,A (a)Turn-off 0 50 100 150 200 0 200 400 600 Time,ns Uds ,V ∆U 0 10 20 30 Id ,A (b)Turn-on

Figure 3.6.: The measured switching behaviour of VSC under inductive load switching (R_{g= 0}Ω).

0 10 20 30 40 50 60 70 80 90 100 0 50 100 150 200 Gate resistance,Ω tf ,ns 0 0.5 1 1.5 2 Etot ,mJ

Figure 3.7.: Impact of gate resistance on switching energy loss and voltage fall time.

current (t_r.i) which is equal to15 ns, it is possible to find the approximate value of total stray inductance in the commutation path [27]. For the current test, the estimated value of L_Σ is equal to 35 nH. Taking into account the value of DC link capacitors ESL (25 nH) and lead inductance of the TO-247 package (7 nH according to [146]), it is possible to conclude that the applied field cancellation techniques are efficient (see Section 3.1).

Using (1.19) and the measured data in Figure 3.6, the total switching energy loss Etot per one com-

mutation can be defined for the designed power core. Together with the sampling frequency of PWM, these values define the switching losses in the VSC. The duration of the turn-on process increases with the value R_g leading to the higher switching losses. As it is discussed in Subsection 1.4.4 and shown in Subsection 2.3.1, the RF spectrum of VSC output voltage is also influenced by the voltage fall time t_f of SiC MOSFET during turn-on. The value of tf is defined between 10% and 90% of the input DC link

voltage [27].

Because the value of E_tot and t_f are essential for the design of VSC and for the EMI analysis, these two values were estimated using the measurements under different values ofR_g. The dependence of the total energy loss per one commutation cycle and voltage fall time during turn-on from the value of gate resistance is shown in Figure 3.7. Both parameters rise linearly with the increase of the gate resistance. The lowest value of20 ns for tf and 0.2 mJ of Etot were achieved with Rg = 0. Increase of the voltage

fall time reduces the amplitudes of RF harmonics in VSC output voltage but at the cost of the switching losses.

Figure 3.8.: The measured output line voltage (DM₁) of designed VSC in the idle mode.

After analysis of the switching process, the designed VSC was operated under PWM with the motor in the idle mode. The phase-to-phase voltage (DM1) was measured to ensure the correctness of the

applied control software. The shape of output PWM voltage under operation with the reference sampling frequency of 24 kHz is shown in Figure 3.8. Due to the relatively high sampling frequency, the pulses can be hardly recognized with the available resolution on the fundamental period of20 ms. However, the curve and its spectrum correspond to the theoretical values of SVPWM presented in [27]. The phase currents, which are presented in Figure 2.12 and Figure 2.12, were obtained with the same PWM voltage during operation with the motor in different modes.

The functionality of the designed VSC (power core) is explored using the measurements in this section. The presented results have also a practical meaning. In Subsection 2.3.1, the voltage shown in Figure 3.8 is analysed in order to improve the spectral representation of voltage sources for the frequency domain models. All rising and falling edges of the considered waveform are evaluated showing the effect of MOSFET and diode commutations described in Subsection 1.4.4. The dependence of MOSFET voltage fall time from gate resistance in Figure 3.7 is used to generate the spectrum of the inverter output voltage under different load conditions (see Figure 2.14). The switching energy loss was also estimated during the measurements to ensure the capability of the applied cooling system of the power core.