The elemental sources were kept in separate heating zones made of high purity graphite.
Each zone was equipped with 6kW halogen lamp heaters and a temperature controller. Separate mass flow controllers controlled the carrier gas (UHP He) flow rate individually through each elemental zone. The reactor setup allowed for specific control of the gas phase Cd/Te stoichiometry and dopant concentration by the adjustment of zone temperature and flow rate.
Each elemental zone was loaded with 99.9999% purity Cd and Te metal sources. The generated vapors were carried forward through separate quartz tubes. After the last elemental zone, a cylindrical graphite tube served as a mixing zone, where the substrate was placed. To avoid vapor condensation before the substrate, the zones were placed in sequence of increasing temperature from the source to the deposition/mixing zone. For example, typical zone temperature for a stoichiometric vapor ratio deposition were – Cd zone 435 ⁰C, Te zone 535 ⁰C and mixing zone 720 ⁰C. The substrate holder was positioned at the edge of the mixing zone to attain a deposition temperature of 580-610 ⁰C. The substrate holder was also equipped with a borosilicate heater, used to preheat the substrate. The depositions were performed in a pressure range of 25-700 Torr. The pressure was controlled by a pressure regulated valve and a mechanical pump. The system parameters such as temperature, flowrate and pressure were controlled and monitored from a computer equipped with a LabVIEW program.
3.2 Cell Fabrication
CdTe solar cells were fabricated in the superstrate configuration. The baseline structure is glass/TCO/CdS/CdTe/Back contact (Figure 3.2). The various components of the cell fabrication steps are discussed in the following sections.
3.2.1 Glass Substrate
Corning Eagle XG, an alkaline earth boro-aluminosilicate glass (alkali-free), was used as the substrate due to its high optical transmittance (up to 90% in the wavelength range 350-2200 nm), mechanical strength and high temperature tolerance. The dimension of the substrates was
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1.45" x 1.32" with a thickness of 0.7 mm. The substrates were thoroughly cleaned under running de-ionized (DI) water following a very short etch in 10% HF solution.
3.2.2 Transparent Conductive Oxide (TCO)
A bilayer of indium tin oxide (ITO) and tin oxide (SnO2) was used as the front contact of the CdTe photovoltaic devices. Both the layers were deposited by RF sputtering in a single system without breaking vacuum in ultra-high purity (UHP) Ar environment. The ITO was the conductive layer with a thickness of 3000 Å, deposited at 250 °C. The SnO2 was used as the buffer layer having a thickness of 1000 Å. The resulting bilayer had a sheet resistance of approx. 8-10 Ω/.
3.2.3 Cadmium Sulfide Window Layer
Cadmium Sulfide (CdS) as the window layer was used as the n-type layer to form the p-n heterojunction with p-type CdTe absorber. Due to the poor electrical properties of CdS, light absorbed in CdS layer does not convert to photocurrent. The CdS layer needs to be as thin as possible, while still thick enough to prevent the formation of pinholes. CdS, in this study, was deposited by the Chemical Bath Deposition (CBD) process on glass/TCO substrates. The process involves the formation of CdS from aqueous alkaline solution of Cd2+ and S2- ions; the sources of the ions were cadmium acetate and thiourea respectively. Ammonium hydroxide (NH4OH) and ammonium acetate (NH4Ac) were the agents used to maintain solution pH balance and control the speed of reaction. The reaction was maintained at ~ 80 °C controlled using a temperature Figure 3.2 CdTe solar cell in superstrate configuration
Glass Substrate TCO n-CdS - Window p-CdTe - Absorber
Back Electrode
+
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bath, while the solution was stirred with a magnetic stirrer to ensure uniform deposition. The reaction steps are the following [101].
NH3 + HOH ↔ NH4+ + OH
-Cd(CH3COO)2 ↔Cd2+ + 2CH3COO-
Cd(NH3)42+ + 2OH- ↔ [Cd(OH)2(NH3)2] + 2NH3
[Cd(OH)2(NH3)2SC(NH2)2] → CdS(S) + CN3H5 + NH3 + 2HOH [Cd(OH)2(NH3)2] + SC(NH2)2 → [Cd(OH)2(NH3)2SC(NH2)2
The reaction was carried out for a duration of 90 min to get an approximate thickness of 90 nm.
3.2.4 Cadmium Telluride Absorber Layer
CdTe in the absorber layer were deposited on glass/TCO/CdS substrates by the EVT outlined in section 3.1. The film thickness was in the range of 4-7 µm.
3.2.5 Cadmium Chloride Heat Treatment
CdCl2 heat treatment (HT), a necessary step for fabricating high efficiency CdTe solar cells, was performed on most devices. In some devices the step was intentionally avoided to isolate its effect from the dopant incorporation. CdCl2 was deposited by thermal evaporation on CdTe surface. The film stack was subsequently annealed under He and O2. The annealing was performed at a temperature varied from 350 °C to 390 °C for 25 mins. After the annealing, the samples were ultra-sonicated in methanol to remove residual CdCl2.
3.2.6 Back Contact
Prior to the back-contact formation, the CdTe films were lightly etched in a Br-methanol solution for 5 seconds. The films were sonicated afterwards in methanol to remove any residue.
This chemical etch removes oxides that may have formed on the CdTe surface during CdCl2
treatment annealing, and it provides a Te-rich p+ layer on the surface. This layer facilitates back contact hole transfer from the CdTe layer due to tunneling.
Two different back contacts were employed in this study. Undoped (i.e. no intentional Cu added) graphite paste was used for Sb and P doped devices to isolate the effect of the dopants.
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For intrinsically deposited devices both undoped and doped graphite paste were used for back contacts. The doped graphite contained Cu doped HgTe. After the back contact application, the devices were annealed in an inert ambient at 275 °C for 20 mins. Strips of indium were used around the devices to facilitate the front contact.
3.3 Characterization
3.3.1 Current-Voltage (JV) Measurement
The open circuit voltage (VOC) and fill factor (FF) of the photovoltaic devices were extracted from Current-Voltage measurements. The measurements were performed inside a solar simulator with intensity calibrated to replicate AM 1.5 condition using a Si reference solar cell. A four-point probe setup to mitigate contact resistance was used with a Keithely 2410 Source meter and the current output was measured as the voltage bias was swept. The data was collected using a LabVIEW program, and the VOC and FF of the devices were calculated.
3.3.2 Spectral Response (SR) Measurement
Spectral response measurements of the devices were performed using an Oriel monochromator (model 74100) to quantify the quantum efficiency (QE) and short circuit current density (JSC) of the cells. The light source for the monochromator was a GE400W/120V Quartz line lamp, and its spectral output was calibrated using a Si reference cell. The current response of the reference and device were measured from 400 nm to 900 nm wavelength. The photon count at each wavelength was calculated from the reference cell response to quantify the QE (see section 1.5.2). The JSC was calculated by integrating the current response using the AM 1.5 spectrum.
3.3.3 Capacitance-Voltage (CV) Measurement
The net doping of the devices was estimated from capacitance-voltage measurements.
The measurements were carried out using a HP 4194A Impedance Analyzer at 10 kHz or 50 kHz frequency with -2 to +0.5 V bias sweep operated from a LabVIEW program. Prior to the CV measurements, the capacitance vs. frequency response of the devices was measured for each
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cell to ensure that there were no significant frequency dispersions present due to deep states and interface states. At high frequencies, CV measurements are affected by external circuit inductance [102]. The measurement frequency was chosen to mitigate both these effects. Net doping vs. distance from junction plot was obtained from the CV data, and the net doping value corresponding to the 0 V bias voltage was used for comparison among devices.
3.3.4 Minority Carrier Lifetime Measurement (TRPL)
Minority carrier lifetimes were measured at National Renewable Energy Laboratory (NREL) facilities with single photon excitation (1PE) Time-Resolved Photoluminescence (TRPL) technique. The carriers were excited from the substrate side through the CdS window layer using a 650 nm excitation laser beam and the resultant photon emission was captured at 840 nm detection wavelength.
3.3.5 Deep Level Transient Spectroscopy (DLTS)
A Sula Technologies Deep Level Spectrometer (Model DDS-12) was employed to analyze the defect distribution of the devices. The sample temperature was varied from 80K to 320K using liquid N2 and heater inside a Janis VPF-100 cryostat. For DLTS measurements, small size CdS/CdTe devices with ~1.5 mm X ~1.5 mm area were fabricated due to the capacitance limit of the DLTS instrument and to reduce contact effects. The devices were screened based on dark JV and CV measurements; the reverse bias leakage current in the dark needed to be less than 100 µA. Temperature sweep above room temperature was avoided in most cases, as it caused permanent change to the defect structure. A bias pulse of -1V to 0V with a pulse width of 1ms was used for the measurements. The capacitance transients due to carrier injection were analyzed with 6 different rate windows from 0.02 to 1 ms. The resultant spectra were analyzed to attain information on trap concentration, activation energy and capture cross section.
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The focus of this study was mainly electrical properties of the CdTe thin films. However, structural properties of select films were analyzed employing Scanning Electron Microscopy (SEM) and X-Ray Diffraction (XRD) to obtain additional information. SEM was performed using a Hitachi S800 system with an accelerating voltage of 25 KV. The crystallographic properties of the films were analyzed using a Panalytical X’pert Pro with a Copper kα source. Film thicknesses were measured on a Dektak 3030ST α-step profilometer.
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