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Using schematics for your top-level or lower-level design files allows you to have a visual representation of your design. You can use schematics for your top-level design, your lower-level design files, or both, as follows:

Top-level schematic

You can use a schematic as your top-level design and create the lower-level modules using any of the following source types: HDL files, state diagrams, CORE Generator™ cores, Architecture Wizard IP, or schematic files. To instantiate a lower-level module in your top-level design, you must create a schematic symbol from the lower-level module, and instantiate the schematic symbol. For more information, see Creating a Top-Level Schematic.

Note: You do not  need to create schematic symbols for CORE Generator cores or for Xilinx® 

Unified Library symbols. The CORE Generator software automatically generates schematic symbols, and library symbols are predefined.

Lower-level schematic

You can use schematics to define the lower-level modules of your design. If the top-level design file is a schematic, you must create a schematic symbol from the lower-level schematic, and then instantiate the symbol in the top-level schematic. If the top-level design file is an HDL file, you must create an HDL instantiation template from the schematic, and then instantiate the template in the top-level HDL file. For more information, see Creating a Lower-Level Schematic.

Entire design composed of schematics

You can create your entire design, including top-level and lower-level modules, using schematics.

The design can be either flat or hierarchical. You must create schematic symbols from the lower-level schematics, and then instantiate them in the top-lower-level schematic design. For more information, see Creating a Top-Level Schematic and Creating a Lower-Level Schematic.

All schematics are ultimately converted to either VHDL or Verilog structural netlists before being passed on to your synthesis tool during the Synthesize process.

Note: For more information on working with schematics in Project Navigator, see the Schematic and Symbol Editors Help. For information on Xilinx Unified Library symbols, see the Components Overview and the Libraries Guides  available from the ISE™ Software Manuals collection. For information on cores, see the Intellectual Property and Cores Overview .

Schematic Design Methods

When using a schematic as your top-level design, use either of the following methods to describe the lower-level modules.

Top-Down Schematic Design Method

Using this method, you create a top-level block diagram description of the design using a schematic. Then, you "push down" into each symbol and define its behavior using an HDL or schematic file. To use this method, do the following:

1. Create your top-level schematic as described in Creating a Project, selecting Schematic as your top-level module type.

2. To create individual top-level blocks for the design, use the Symbol Wizard, as described in Creating a Symbol. When using the Symbol Wizard, ensure that you use the following default settings:

Pin Name Source: Specify Manually Shape: Rectangle

Note: The Symbol Wizard allows you to add input, output, or bidirectional pins. You can create bus (multi-signal) pins using parentheses, for example: inbus(7:0).

After you click Finish, the symbol is added to the local symbol library for the project and it opens in the Project Navigator Workspace. If needed, you can edit the symbol in the Workspace.

3. In the Project Navigator Workspace, click the tab for your top-level schematic.

4. Instantiate your new symbol in the top-level schematic, as described in Adding a Symbol Instance.

5. Right-click the symbol you added, and select Symbol > Push into Symbol.

6. You are prompted to create one of the following template file types:

Schematic

The schematic contains I/O markers that correspond to the pins in the block symbol you created.

Build the schematic by adding symbols as described in Adding a Symbol Instance. You can use Xilinx® Unified Library symbols or symbols that you create.

VHDL or Verilog

The template contains the HDL port descriptions that correspond to the pins in the block symbol you created. You can then add the behavior of the module. The ISE Language Templates provide a convenient method for you to insert pre-built language and functional code samples into your HDL file. For details, see Working with Language Templates .

Note: The next time you use the Push into Symbol command, the HDL or schematic file opens in the Project Navigator Workspace.

7. Complete your top-level schematic, starting with step 2 in Creating a Top-Level Schematic.

Bottom-Up Schematic Design Method

Using this method, you create a top-level schematic design and then create lower-level functional blocks to instantiate in the top-level design using either HDL source files or a schematic composed of Xilinx unified library symbols. To use this method, do the following:

1. Create your top-level schematic as described in Creating a Project, selecting Schematic as your top-level module type.

2. To create lower-level modules, create a new source file as described in Creating a Source File, selecting one of the following file types:

ABEL-HDL Module (CPLDs only)

After you click Finish, the HDL file is added to the project and opens in the Project Navigator Workspace. You can then define the behavior of the module. The ISE Language Templates provide a convenient method for you to insert pre-built language and functional code samples into your HDL file. For details, see Working with Language Templates .

IP

If you selected a CORE Generator core, the CORE Generator software opens and allows you to define your core. For details, see the CORE Generator Help. If you selected an Architecture Wizard core, the Architecture Wizard tool opens and allows you to define your core. For information, click the More Info buttons in the Architecture Wizard.

Schematic

After you click Finish, the schematic file is added to the project and opens in the Project Navigator Workspace. Build the schematic by adding symbols as described in Adding a Symbol Instance. You can use Xilinx Unified Library symbols or symbols that you create.

State Diagram

After you click Finish, the StateCAD software displays in which you can create your state machine.

For details, see Working with State Machines . Verilog Module or VHDL Module

Optionally, you can use the New Source Wizard to predefine the modules ports, which ensures that the appropriate port definitions appear in the HDL file. After you click Finish, the HDL file is added to the project and opens in the Project Navigator Workspace. Define the behavior of the module.

The ISE Language Templates provide a convenient method for you to insert pre-built language and functional code samples into your HDL file. For details, see Working with Language Templates . 3. In the Module View tab of the Sources in Project window, select the lower-level module file.

4. Create a schematic symbol from the lower-level module, as described in Creating a Schematic Symbol.

Note: You do not need to convert CORE Generator cores to schematic symbols, because the CORE Generator software automatically generates schematic symbols.

5. Instantiate your new symbol in the top-level schematic as described in Adding a Symbol Instance.

6. Complete your top-level schematic design, starting with step 2 in Creating a Top-Level Schematic.

Schematic and Symbol Editor Tips

For general tips in creating schematics, see Schematic Design Tips. Following are tips for working with the Schematic and Symbol Editors:

To update all the schematics in your design with current symbols from your symbol directories, run the Update All Schematic Files process. If you edit a symbol, you must run this process. For details, see Updating All Schematic Files in your Design .

To change the color scheme of the Schematic and Symbol Editors, use Edit > Preferences. For details, see Setting Color Preferences.

To Zoom In on a schematic or symbol,press Ctrl and drag the mouse down and to the right. To Zoom Out, press Ctrl and drag the mouse up and to the left. For details, see Zooming.

To change the sheet size, click the schematic background, and select Edit > Object Properties.

For details, see Resizing a Sheet.

To rename a net, right-click the net and select Rename Selected Net. You can rename a single branch of a net or the entire net. For details and alternate methods, see Naming a Net.

To quickly add I/O markers and connecting wires to the symbol pins, select Add > I/O Marker and then use the mouse to drag a selection box around either the input or the output pins of the symbol.

For alternate methods, see Adding an I/O Marker.

To quickly find all branches of a net even if they are not visibly connected, select Tools > Query.

For details, see Running a Query.