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Figure 5.14 shows the overall TDC structure. A global phase-locked loop in the analog domain and a coarse counter in the digital domain are employed to generate the timestamps, which are distributed to all 36 channels. When the channel-wise trigger signal arrives, the timestamps are sampled and stored in their corresponding local latches, including the TDC latches in the analog domain and the DFFs (D-flip flops) in the digital domain. The states of the latches are then processed in the digital domain to extract and store the timing information in a binary representation. As shown in Figure 5.15, the overall TDC timestamps consists of three stages, denoting as fine counter (FC), middle counter (MC), and coarse counter (CC).

The first stage timestamps are provided by the voltage-controlled oscillator (VCO) of the PLL. The ring VCO consists of 16 identical delay cells, of which the cell delay τdis tunable by

a control voltage V_ctrl. The oscillator clock signal that propagates through the cells is inverted after 16τ_d in the last element and then fed back to the first delay cell. After another delay of 16τd, the VCO will return to its previous state. In this way, the VCO runs at the period of

32τd, and the states of the delay cells provide the fine-time interpolation of the VCO clock.

The control voltage V_ctrl is generated by the PLL feedback loop, which consists of clock divider, phase-frequency detector (PFD), charge pump, and low-pass filter. In the locked state, the feedback clock of the divider output has the same frequency as that of the 40 MHz

clock buffers PLL Digital domain τd τd 16 cells τd τd 160 MHz 40 MHz system clock

Loop Filter Charge Pump PFD

Divider coarse counter

Vctrl FINE CNT MIDDLE CNT COARSE CNT TDC Latch TDC Latch DFF Global Channel-wise TDC Logic Dout Trigger Logic trigger

Figure 5.14: Overall PLL-based TDC structure. trigger signal is from the hit-logic circuit in Figure 5.7. Dout goes to post-processing stage of the digital part. The counters in dashed

VCO CLK-0 VCO CLK-1 VCO CLK-2 VCO CLK-13 VCO CLK-14 VCO CLK-15 FC[4:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 (a) VCO CLK-15 MC[2:0] 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 DIV CLK CC[19:0] 000 001 010 011 (b)

Figure 5.15: Working principle of the PLL-based TDC in the KLauS ASIC. (a) 1-st stage timestamps from fine counter by the VCO delay cells providing time interpolation of the VCO clock. (b) 2-nd stage timestamps from the middle counter driven by the VCO clock and 3-rd stage timestamps from the coarse counter driven by the feedback clock.

input reference clock. Given a division factor of 4, the VCO clock is thereby running on a frequency of 160 MHz, providing a cell delay of τ_d= 1/32fvco≈ 200 ps.

The 16 output clocks of the VCO delay cells are buffered and fanned out to all channels. Upon the arrival of the trigger signal, the instant values of the 16 clocks are latched in a thermometer code (or Unary code [100]). The recorded codes are then converted into its corresponding 5-bit binary code in the TDC logic circuit as the fine counter (FC) value, as illustrated in Figure 5.15(a). The 5-bits fine counter thereby has a bin-size of τ_d ≈ 200 ps and a range of 32τd= 6.25 ns.

The state of the clock divider can be treated as a counter of the 160 MHz VCO clock, provid- ing another level of fine-time interpolation of the feedback clock, as shown in Figure 5.15(b). Although there are only 2 bits extra information provided by these states, it is desirable to have one more bit for redundancy to avoid the misalignment between the 1-st and 2-nd timestamp stages when the delay of the divider is taken into consideration. Three intermediate clocks by the divider are fanout to all channels, counting the edge numbers of the VCO clock. The 3-bits middle counter has an average bin-size of 16τ_dand an exact range of T0 = 128τd= 25 ns, where

T0 is the period of the reference clock.

In the 3rd stage, a 20-bit coarse counter is implemented in the digital domain and provides the coarse timing information. This counter is driven by both edges of the feedback clock from

the divider, providing another 1-bit redundancy. In this way, the coarse counter has a bin-size of T0/2 = 12.5 ns and a range of up to 13 ms.

Owing to the use of the PLL, the phase error between the reference and feedback clock is negligible or at least constant over time. Therefore, this TDC structure allows synchronizing multiple PLLs to an external reference clock and provides a common time reference to multiple ASICs. Nevertheless, the feedback clock given by the divider instead of the reference clock is used to drive the coarse counter to avoid the misalignment between the first two timestamp stages to the 3-rd stage due to the potential phase error.

The 2-bits redundancy are removed in the TDC Logic circuit, which loads the latched times- tamps at the rising edge of busy (see Figure 5.8). The binary-coded timestamps D_out from TDC logic is moved out for temporary storage along with the ADC output.

Compared to the DLL-structure where 128 clock signals from VCDL need to fan out to all channels, this PLL-based solution with a divider of 4 only needs to distribute 16 clock signals from VCO and 3 analog counter signals for the fine-time interpolation. Therefore, only 38 lines are needed when all the signals are routed differentially, which could greatly save the power and silicon area. However, there are always arguments that the DLL-based TDC provides superior jitter performance compared to the PLL-based approach, which suffers from the accumulation jitter from the VCO. Fortunately, the impacts of this inherent jitter could be optimized by carefully designing the loop dynamic parameters of the PLL. In the next subsection, the analysis and design of the PLL will be presented.