LOCALIDAD DE ESTUDIO

The TriCore supports 16 and 32-bit instructions. Since there is no mode bit and no require- ment for word alignment of the 32-bit instructions we can freely mix the instructions. To specify a 16-bit command, the basic operation name is followed by a 16, e. g., SH16. The advantage of a 16-bit instruction is, that it is smaller than a 32-bit instruction in the program memory. It should be used whenever possible for smaller code size.

To follow the upcoming assembler examples, we first show how an assembler instruction is composed. The assembler instruction starts with the basic operation, which is derived from the intention of the instruction. For example, a shift instruction starts with SH. The basic operation can be followed by an operation modifier, e. g., the instruction JNE would execute a conditional jump. The condition here is given by the NE, which stands for “not equal”. In Table 5.1 we list all operation modifiers used by us.

Operation Modifier Name Description Example

C Carry Use and update carry bit ADDC

S Saturation Saturate result ADDS

EQ Equal Comparison equal JEQ

GE Greater than Comparison greater than or equal JGE

A Absolute Absolute (jump) JLA

I Immediate Large immediate ADDI

LT Less than Comparison less than JLI

NE Not equal Comparison not equal JNE

D Decrement Decrement counter JNED

I Increment Increment counter JNEI

Z Zero Use zero immediate JNZ

Table 5.1: Operation Modifiers

The data type modifier specifies the data type we want to work with. For example, if we load a byte from memory, we use the LD.B instruction. The .B denotes, that we load a byte value. In Table 5.2 we list the modifier for the individual data types:

The data type modifiers can be combined to a new one, e. g., the instruction LD.BU loads an unsigned byte. In the following subsections, we will describe the commonly used assembler instructions.

5.3.1 Load and Store Instructions

To load and store a value into data register D[A] we can use the load word and store word instructions (LD.W and ST.W).

LD.W D[a], offset ; Load Word (Absolute

Data Type Modifier Name Example .D Double-word LD.D .W Word EQ.W .A Address ADD.A .H Half-Word ADD.H .B Byte ADD.B .T Bit AND.T .U Unsigned ADDS.U

Table 5.2: Data Type Modifiers

LD.W D[a], A[b], offset ; Load Word (Base + Short

; Offset Addressing)

ST.W off, D[a] ; Store Word

5.3.2 Arithmetic Instructions

The following three bit arithmetic instruction work almost the same way. So we describe it only once. The OR,XOR and AND instruction computes the bitwise OR, XOR, respectively AND operation of the data register D[a] and the data register D[b]. The result is stored in the data register D[c].

OR D[c], D[a], D[b] ; c = a OR b

XOR D[c], D[a], D[b] ; c = a XOR b

AND D[c], D[a], D[b] ; c = a AND b

The multiplication instruction multiplies two signed 32-bit values from the data register D[a]and the data register D[b] and puts the product into the 32-bit data register D[c] or the 64-bit data register E[c].

MUL D[c], D[a], D[b] ; c = (lower half of)

; a * b

MUL E[c], D[a], D[b] ; c = a * b

With the shift instruction SH we can shift the value in D[a] by the number of bytes specified with either a constant value const or the value in data register D[b]. The result is put in D[c]. The vacated bits are filled with zeros and the bits shifted out are discarded.

SH D[c], D[a], D[b] ; shift D[a] by D[b] positions

; and store the result in D[c]

SH D[c], D[a], const ; shift D[a] by #const positions

5.3.3 Extract Instruction

It is possible to work with so called bit-fields. We can extract the number of consecutive bits specified by width starting at the bit pos from a source register D[a] with the EXTR (Extract Bit Field) and EXTR.U (Extract Bit Field Unsigned) instructions, beginning with the bit number specified by the pos operand. The result is stored sign extended (EXTR) or filled with zeros (EXTR.U) in the destination register D[c]. Figure 5.4 denotes the EXTR.U operation.

EXTR D[c], D[a], pos, width ; Extract Bit Field

EXTR.U D[c], D[a], pos, width ; Extract Bit Field Unsigned To extract a 32-bit word from the registers {D[a] and D[b]}, where D[a] contains the most-significant 32 bits of the value, we use the DEXTR instruction. The extraction starts at the bit number specified with 32-pos. The result is put in D[C].

DEXTR D[c], D[a], D[b], pos ; Extract from Double Register

Figure 5.4: Operation of the EXTR.U instruction, source:[Inf07]

Packed Arithmetic

The packed arithmetic instruction partitions a 32-bit word into four byte values or into two, 16-bit halfwords values. Those can be fetched, stored, and operated on in parallel. The packed byte format is denoted in Figure 5.5. Instructions which operate on the data in this way are denoted by the .B and .BU data type modifier. The arithmetic on packed data includes addition, subtraction, multiplication, shift and the absolute difference.

Figure 5.5: Packed Byte Data Format, source:[Inf07]

To load the contents of the memory location specified by the offset we can use the load byte instruction (LD.B).

LD.B D[a], offset ; Load Byte (Absolute ; Addressing)

LD.B D[a], A[b], offset ; Load Byte (Base + Short

; Offset Addressing)

The ST.B instruction stores the byte value in the eight least-significant bits of the data register D[a] to the byte memory location specified by the offset off.

ST.B off, D[a] ; Store Byte

5.3.4 Address Arithmetic

The ADDSC.A operation left-shifts the contents of data register D[a] by the amount specified by n, where n = 0,. . . ,3. That value is added to the contents of address register A[b] and the result is put into address register A[c].

ADDSC.A A[c], A[a], D[a], n ; Add Scaled Index to ; Address

The LEA instruction computes the effective address and puts the result in address register A[a].

LEA A[a], offset ; Absolute Addressing

; Mode

LEA A[a], A[b], offset ; Base + Short Offset

; Addressing Mode