Cross-sections exhibiting quantum resonances: the B + OH case
2. Potential-energy surface and method numerical parameters
6.4 eV well located early in the entrance channel can be formed, from which the minimum-energy path
All of our experiments are carried out using SPICE simulations on a 65-nm technolo-gy process. We use Monte Carlo method to simulate the effect of process variations and environmental variations. In our simulation, we set up the transistor parameters and process variations based on a major industrial standard model. Each proposed structure has been simulated over at least 20 Monte Carlo runs in SPICE. The simulated MUX based Physically Unclonable Functions all have 100 stages. Accordingly, we need to apply a 100-bit challenge to the PUF to produce a 1-bit response, and we apply 100 different challenges to generate the final 100-bit digital signature for each IC.
Measuring inter-chip variations: The inter-chip variations were determined by comparing the digital signature of each IC to each other and calculate the Hamming Distance between the two signatures. Since we had 20 chip instances, we had 20*19/2,
30 i.e., 190 possible digital signature comparisons. We use the maximum and the minimum of these numbers as measures of the inter-chip variation.
Measuring intra-chip variations: The intra-chip variations were determined by comparing the digital signal processing of the same IC under different environmental conditions. In our case, we use temperature as the primary factor. We also simulated the intra-chip variations under different voltages, from 1V to 1.2V . However, it is shown that the intra-chip variations introduced by different temperatures from 0oC to 100oC were more significant compared to the intra-chip variations caused by voltage variations. The digital signatures of the PUF at 0oC, 20oC, 40oC, 80oC, 100oC were obtained; however, we only present the comparisons of Hamming Distance between 0oC and 100oC, as those exhibit the largest variations. We simulated 10 different CRPs for each IC, and simulated 20 different IC instances. Therefore we have 200 comparisons in total. We provide the maximum and the average of the Hamming distances for the intra-chip variations.
Simulation circuit structures: As presented in the previous section, we simulated the digital signature for each proposed Physical Unclonable Function structure. We add 10 feed-forward arbiters for each feed-forward PUF. For instance, the feed-forward arbiters are from stage 1 to stage 11, from stage 11 to stage 21 ... from stage 91 to stage 100 in a feed-forward cascade structure. The feed-forward arbiters are from stage 1 to stage 7, from stage 11 to stage 17 ... from stage 91 to stage 97 in feed-forward overlap structure. In a feed-forward cascade structure, the feed-forward arbiters are from stage 1 to stage 51, from stage 6 to stage 56 ... from stage 46 to stage 96.
For the reconfigurable feed-forward structure, we also add 10 such arbiters and MUX structures into the original PUF circuit, which can switch among the 3 different feed-forward structures. Moreover, we also simulated 10 DeMUX components in the MUX and DeMUX PUF, the inputs and the outputs of the DeMUXs are from stage 3 to stage 8, from stage 13 to stage 18 ... from stage 93 to stage 98. Finally, we simulated 20 parallel MUX PUFs for the output recombination structure. Therefore, we have 40
paths in total, and we derived the digital signature by comparing adjacent paths. In other words, the delay of the first path was compared with that of the second path, which is the same as a single PUF. The delay of the second path was compared with that of the third path, and so on. Finally, the delay of the 39th path was compared with that of the 40th path. Therefore, except for the first and the last paths, each path was compared to two other paths.
Measuring reconfigurability: We randomly choose the configure data of the different structures, and then fix the configure data when examining the inter-chip variations and the intra-chip variations. However, when we add the reconfigurable components into the circuits, the challenge-bit lengths are decreased; therefore, we need to adjust the challenge bits when simulating these reconfigurable structures. To test the reconfigurability, we simply fix the challenge bits, but change the configure data to compare the digital signatures. All the simulations were carried out under the environmental condition of 25oC and 1.1V .
Table 2.1 presents the inter-chip variations and intra-chip variations for different MUX Physical Unclonable Function structures. First, it can be observed that the min-imum inter-chip variation is larger than the maxmin-imum intra-chip variation for all of the simulated structures. Thus, we can conclude that the variations caused by the random-ness in manufacturing process are more significant than the variations under different environmental conditions. Therefore, these PUFs can be used as reliable secret keys with some error correcting techniques. Second, it can also be observed that by adding feed-forward arbiters into the MUX PUF circuit, the inter-chip variations and intra-chip variations are both increased, since the noise can have influence on the select signals of some intermediate stages. By comparing the inter-chip variations and the intra-chip variations, we conclude the feed-forward separate structure is the most reliable struc-ture while the feed-forward cascade is the least reliable one among the 3 feed-forward structures. The reconfigurable feed-forward structure has very close performance to the 3 types of feed-forward structures, since its functionality is switching among the 3.
32 Moreover, the reconfigurable DeMUX and MUX PUF has similar inter-chip variation as the non-feed-forward structure, but the intra-chip variation is increased, as the number of stages is reduced by some configurations. Therefore, the reliability of this structure is decreased.
Table 2.1: Simulation Results: Variations
Inter-chip Variation Intra-chip Variation
Structures Max Min Max Avg
Non-feed-forward 59 22 13 5.8
Feed-forward Overlap 66 27 15 8.7
Feed-forward Cascade 64 25 20 10.7
Feed-forward Separate 65 26 17 9.9
Reconfigurable Feed-forward 65 25 19 10.3
MUX and DeMUX 57 23 16 7.1
Table 2.2 shows the reconfigurability of each reconfigurable structure. It can be seen that the output recombination structure has the best reconfigurability, that is, by fixing the challenge bits and only changing the configure data, the digital signature would vary most significantly. In our simulation result, the average variation is 38.7 bits. The MUX and DeMUX PUF exhibits the least reconfigurability; that is because the func-tion of the DeMUX is only to determine whether to skip some stages or not. When the process variations of other stages are relatively large, the difference of digital signatures with two different configure data may only vary a little bit. For output recombination structure, it is similar to comparing different paths with different configurations, so its performance is close to the inter-chip variation of the non-feed-forward MUX PUF. It also can be observed that although the challenge hash structure and the challenge LFSR structure both pre-process the challenge before it is applied to the circuit, their recon-figurability still have some difference. As the challenge LFSR appears to have better reconfigurability, we can conclude that the number generated by the LFSR in our case may have better randomness than that of the Hash Function. Finally, the proposed reconfigurable feed-forward MUX PUF has the average Hamming distance 32.4 bits by
different configurations, which will be sufficient to be used as a secure and reliable secret key storage method, considering its complex and nonlinear functionality.
Table 2.2: Simulation Results: Reconfigurability Variation
Structures Max Avg Min
Challenge LFSR 44 34.6 28
Challenge Hash 42 28.3 19
Output recombination 57 38.9 25 Reconfigurable Feed-forward 47 32.4 22
MUX and DeMUX 33 24.7 13
Overall, all the proposed reconfigurable structures have considerable reconfigurabili-ty, and can be used for reliable authentication and identification within certain error tol-erance, as the minimum of the inter-chip variations would be larger than the maximum intra-chip variation. The output recombination structure has the best reconfigurable ability; however, we consider the reconfigurable feed-forward MUX PUF to have the best performance due to its security, as it is extremely hard to be modeled by certain linear modeling methods.
2.6 Conclusion
We have presented several reconfigurable silicon MUX Physical Unclonable Function-s baFunction-sed on two major approacheFunction-s and demonFunction-strated their effectiveneFunction-sFunction-s by experimental results via inter-chip variation and intra-chip variation. We also have discussed the reliability perspective of PUFs and proposed several methods to increase the security.