Longitud de Brote

TEOC 1. SWE (status word enable)

2. TBMT (transmit buffer empty)

3. Parallel data (TD7-TD0)

4. TDS (transmit data strobe)

5. TSO (Transmit

end of

character) _(Transmit serial data)

FIGURE 14 UART transmitter signal sequence

data. When the CPU senses an active condition of TBMT, it applies a parallel data char- acter to the transmit data lines (TD7 through TD0) and strobes them into the transmit

buffer register with an active signal on the transmit data strobe signal. The con- tents of the transmit buffer register are transferred to the transmit shift register when the

transmit end-of-character (TEOC) signal goes active (the TEOC signal is internal to the

UART and simply tells the transmit buffer register when the transmit shift register is empty and available to receive data). The data pass through the steering logic circuit, where it picks up the appropriate start, stop, and parity bits. After data have been loaded into the transmit shift register, they are serially outputted on the transmit serial output (TSO) pin at a bit rate equal to the transmit clock (TCP) frequency. While the data in the transmit shift register are serially clocked out of the UART, the CPU applies the next char- acter to the input of the transmit buffer register. The process repeats until the CPU has transferred all its data.

10-1-2 UART receiver. A simplified block diagram for a UART receiver is shown in Figure 15. The number of stop bits and data bits and the parity bit parameters specified for the UART receiver must be the same as those of the UART transmitter. The UART re- ceiver ignores the reception of idle line 1s. When a valid start bit is detected by the start bit verification circuit, the data character is clocked into the receive shift register. If parity is used, the parity bit is checked in the parity checker circuit. After one complete data char- acter is loaded into the shift register, the character is transferred in parallel into the receive buffer register, and the receive data available (RDA) flag is set in the status word register. The CPU reads the status register by activating the status word enable signal and, if RDA is active, the CPU reads the character from the receive buffer register by placing an active signal on the receive data enable (RDE) pin. After reading the data, the CPU places an active signal on the receive data available reset pin, which resets the RDA pin. Meanwhile, the next character is received and clocked into the receive shift register, and the process repeats until all the data have been received. Figure 16 shows the receive signaling sequence that occurs between the CPU and the UART.

10-1-3 Start-bit verification circuit. With asynchronous data transmission, pre- cise timing is less important than following an agreed-on format or pattern for the data. Each transmitted data character must be preceded by a start bit and end with one or more

1RDAR2

1SWE2 1TDS2

Start bit verification circuit RSI input data from modem RCP (receive clock) Parity checker circuit Control register

Receive shift register

Receive buffer register

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

Status word register

RPE RFE RDA

RDA RDE

Parallel output data

ROR SWE RDAR

FIGURE 15 UART receiver block diagram

Central processing unit (CPU) UART Receiver 3. SWE (status word enable)

5. SWE (status word enable)

7. RDE (receive data enable)

9. RDAR (receive data available

reset)

1. Valid start bit detected

2. Receive data character loaded serially into receive shift register 4. RDA (receive data available)

6. Status word transfered to CPU

8. Parallel data (RD7-RD0) RSI serial data received from modem (RPE, RFE, and ROR)

FIGURE 16 UART receive signal sequence

stop bits. Because data received by a UART have been transmitted from a distant UART whose clock is asynchronous to the receive UART, bit synchronization is achieved by es- tablishing a timing reference at the center of each start bit. Therefore, it is imperative that a UART detect the occurrence of a valid start bit early in the bit cell and establish a timing reference before it begins to accept data.

The primary function of the start bit verification circuit is to detect valid start bits, which indicate the beginning of a data character. Figure 17a shows an example of how a noise hit can be misinterpreted as a start bit. The input data consist of a continuous string

Fundamental Concepts of Data Communications

Idle line 1s

1X RCP

Samples data high – idle line 1

Samples data detects low invalid start bit

(a) Samples data interprets b0 as a logic 1 Samples data interprets b1 as a logic 1 Noise impulse

Idle line 1s misinterpreted as data

Idle line 1s

16X RCP

Noise impulse

wait 7 clock pulses before sampling again

1 2 3 4

Sample after 7 clock cycles high – invalid start bit

(b) 5 6 7

Idle line 1s (ignored)

Idle line 1s Start bit b0 b1

bit b1 = 0

bit b0 = 1

Sample again still low valid start bit Detects

low 16X RCP

Wait 16 clock pulses sample data Wait seven

clock pulses

Wait 16 clock pulses sample data

FIGURE 17 Start bit verification: (a) 1X RCP; (b) 16X RCP; (c) valid start bit (c)

Idle line 1s _{Center of start bit Center of bit b} 0 Center of bit b1 bit b1 = 0 bit b0 = 1 Sample again still low valid start bit

Sampling error Sampling error Sampling error Detects low 16X RCP Detection error

Wait 16 clock pulses sample data Wait seven

clock pulses

Wait 16 clock pulses sample data

FIGURE 18 16X receive clock rate

of idle line 1s, which are typically transmitted when there is no information. Idle line 1s are interpreted by a receiver as continuous stop bits (i.e., no data). If a noise impulse occurs that causes the receive data to go low at the same time the receiver clock is active, the receiver will interpret the noise impulse as a start bit. If this happens, the receiver will misinterpret the logic condition present during the next clock as the first data bit (b0) and the follow-

ing clock cycles as the remaining data bits (b1, b2, and so on). The likelihood of misinter-

preting noise hits as start bits can be reduced substantially by clocking the UART receiver at a rate higher than the incoming data. Figure 17b shows the same situation as shown in Figure 17a, except the receive clock pulse (RCP) is 16 times (16) higher than the receive serial data input (RSI). Once a low is detected, the UART waits seven clock cycles before resampling the input data. Waiting seven clock cycles places the next sample very near the center of the start bit. If the next sample detects a low, it assumes that a valid start bit has been detected. If the data have reverted to the high condition, it is assumed that the high- to-low transition was simply a noise pulse and, therefore, is ignored. Once a valid start bit has been detected and verified (Figure 17c), the start bit verification circuit samples the in- coming data once every 16 clock cycles, which essentially makes the sample rate equal to the receive data rate (i.e., 16 RCP/16  RCP). The UART continues sampling the data once every 16 clock cycles until the stop bits are detected, at which time the start bit ver- ification circuit begins searching for another valid start bit. UARTs are generally pro- grammed for receive clock rates of 16, 32, or 64 times the receive data rate (i.e., 16, 32, and 64).

Another advantage of clocking a UART receiver at a rate higher than the actual re- ceive data is to ensure that a high-to-low transition (valid start bit) is detected as soon as possible. This ensures that once the start bit is detected, subsequent samples will occur very near the center of each data bit. The difference in time between when a sample is taken (i.e., when a data bit is clocked into the receive shift register) and the actual center of a data bit is called the sampling error. Figure 18 shows a receive data stream sampled at a rate 16 times higher (16 RCP) than the actual data rate (RCP). As the figure shows, the start bit is not immediately detected. The difference in time between the beginning of a start bit and when it is detected is called the detection error. The maximum detection er- ror is equal to the time of one receive clock cycle (tcl  1/Rcl). If the receive clock rate

equaled the receive data rate, the maximum detection error would approach the time of one bit, which would mean that a start bit would not be detected until the very end of the bit time. Obviously, the higher the receive clock rate, the earlier a start bit would be detected.

Idle line 1s 8X 1 2 3 b0 Detects low Sampling error Center of start bit

(Wait 3 clocks before sampling again)

(a) Idle line 1s 16X 1 2 3 4 5 6 7 b0 Detects low Sampling error

Center of start bit

(b) (Wait 7 clocks before sampling again)

FIGURE 19 Sampling error: (a) 8X RCP; (b) 16X RCP

Because of the detection error, successive samples occur slightly off from the center of the data bit. This would not present a problem with synchronous clocks, as the sampling error would remain constant from one sample to the next. However, with asynchronous clocks, the magnitude of the sampling error for each successive sample would increase (the clock would slip over or slip under the data), eventually causing a data bit to be either sam- pled twice or not sampled at all, depending on whether the receive clock is higher or lower than the transmit clock.

Figure 19 illustrates how sampling at a higher rate reduces the sampling error. Figures 19a and b show data sampled at a rate eight times the data rate (8) and 16 times the data rate (16), respectively. It can be seen that increasing the sample rate moves the sample time closer to the center of the data bit, thus decreasing the sampling error.

Placing stop bits at the end of each data character also helps reduce the clock slip-

page (sometimes called clock skew) problem inherent when using asynchronous trans-

mit and receive clocks. Start and stop bits force a high-to-low transition at the beginning of each character, which essentially allows the receiver to resynchronize to the start bit at the beginning of each data character. It should probably be mentioned that with UARTs the data rates do not have to be the same in each direction of propagation (e.g., you could transmit data at 1200 bps and receive at 600 bps). However, the rate at which data leave a transmitter must be the same as the rate at which data enter the receiver at the other end of the circuit. If you transmit at 1200 bps, it must be received at the other end at 1200 bps.

10-2 Universal Synchronous Receiver/Transmitter

A universal synchronous receiver/transmitter (USRT) is used for synchronous transmis- sion of data between a DTE and a DCE. Synchronous data transmission means that a syn- chronous data format is used, and clocking information is generally transferred between the DTE and the DCE. A USRT performs the same basic functions as a UART, except for

synchronous data (i.e., the start and stop bits are omitted and replaced by unique synchro- nizing characters). The primary functions performed by a USRT are the following: