LUGAR DE EJECUCIÓN

The connection primitives are used to anchor the interface signals. However, after placement and routing, they are no longer required, because the interface signals are bound to the proper wires at this point. We constrain the placement of connec- tion primitives within the partial area. The reason is that we reconfigure the partial area with modules during run-time, and therefore we have no logic overhead due to these connection primitives. This concept is demonstrated in Figure 5.3. As illustrated in Figure 5.3a, the connection primitives (LUTs) within the partial area are used to anchor the interface signals. Then, when we configure a module, the connection primitives are reconfigured by the logic of the module, as illustrated in Figure 5.3c. Therefore, the connection primitives do not cause any logic overhead to the system.

In Vivado, we constrain the placement of the connection primitives by using pblocks [33]. A pblock is a user-chosen area on the FPGA fabric. Logic cells (e.g., FFs and LUTs) can be assigned to the pblock. By default, the placement of the logic cells belonging to the pblock is within its region.

By using GoAhead, we create a pblock on the same location as the partial area and assign the connection primitives to the pblock. By doing this, we constrain the placer to place all the connection primitives within the partial area. Another placement constraint is that logic belonging to the static part of the system should be placed outside the partial area. For this purpose, we use the property EX-

CLUDE PLACEMENT on the same pblock that we used to constrain the placement

of the connection primitives [32]. This property forces the placement of the logic cells that do not belong to the pblock outside the pblock region. Therefore, logic cells that belong to the static part of the system will not be placed within the partial area.

The commandsPrintAreaConstraint andPrintExcludePlacementProperty The commands that we use in GoAhead to generate the placement constraints are

PrintAreaConstraintandPrintExcludePlacementProperty. The syntax of these com-

mands is illustrated in Listing 5.12. The command PrintAreaConstraint creates a TCL script that defines a pblock in Vivado. The size and location of this pblock de- pend on the current selection of tiles in GoAhead. Therefore, we have to select the tiles of the partial area before we apply this command, as illustrated in Listing 5.12.

The commandPrintExcludePlacementProperty generates a TCL script that ap- plies theEXCLUDE PLACEMENT property on the pblock. Note thatAppend is set toFalsein the commandPrintAreaConstraint and set toTruein the commandPrint-

5.2. IMPLEMENTING THE STATICSYSTEM 71 Consequently, we avoid the generation of many separate files.

1 # s e l e c t the p a r t i a l a r e a 2 C l e a r S e l e c t i o n; 3 S e l e c t U s e r S e l e c t i o n U s e r S e l e c t i o n T y p e= P a r t i a l A r e a ; 4 5 # p l a c e l o g i c c e l l s of the p a r t i a l a r e a w i t h i n the p a r t i a l a r e a 6 P r i n t A r e a C o n s t r a i n t 7 I n s t a n c e N a m e= i n s t _ P a r t i a l A r e a 8 F i l e N a m e=./ s t a t i c _ p l a c e m e n t _ c o n s t r a i n t s . tcl 9 A p p e n d= F a l s e 10 C r e a t e B a c k u p F i l e= T r u e ; 11 12 # p l a c e all o t h e r l o g i c c e l l s o u t s i d e the p a r t i a l a r e a 13 P r i n t E x c l u d e P l a c e m e n t P r o p e r t y 14 I n s t a n c e N a m e= i n s t _ P a r t i a l A r e a 15 F i l e N a m e=./ s t a t i c _ p l a c e m e n t _ c o n s t r a i n t s . tcl 16 A p p e n d= T r u e 17 C r e a t e B a c k u p F i l e= T r u e ;

Listing 5.12: The commands PrintAreaConstraint and PrintExcludePlacement- Property are used to (1) constrain the logic cells of the partial area being placed within the partial area and (2) exclude placement of logic cells from the static part of the system within the partial area.

The TCL Commands

The GoAhead commands in Listing 5.12 generate a TCL script that constrains the placement of the logic cells. This TCL script is illustrated in Figure 5.13. First, the pblock is defined by the command create pblock. Then, we use the command resize pblock to place the pblock onto the fabric of the FPGA. In this command, we also specify the location and the size of the pblock.

In the following, we add the logic cells to the pblock by using the command add cells to pblock. We use the commandget cells to obtain all the logic cells from a component instantiation in VHDL. As described in Section 5.2.3, the partial area component contains all the connection primitives. Therefore, we add the logic cells of the partial area to the pblock. Consequently, we assigned all the connection prim- itives to the pblock. Finally, we apply the propertyEXCLUDE PLACEMENT on this pblock.

72 CHAPTER 5. IMPLEMENTATION Note that the instantiation name of the partial area component is specified by the parameterInstanceNamein the GoAhead commandPrintAreaConstraint. Also, the name of the pblock is based on this parameter. Therefore, the parameter In-

stanceName must be the same in both commandsPrintAreaConstraint and Print-

ExcludePlacementProperty. By doing this, we apply the generated commands and

properties in the TCL script on the same pblock.

1 c r e a t e _ p b l o c k p b _ i n s t _ P a r t i a l A r e a ; 2 # d e f i n e l o c a t i o n and s i z e of the p b l o c k 3 r e s i z e _ p b l o c k [g e t _ p b l o c k s p b _ i n s t _ P a r t i a l A r e a ] 4 -add { S L I C E _ X 3 6 Y 0 : S L I C E _ X 4 7 Y 9 9 }; 5 # add l o g i c c e l l s to the p b l o c k 6 a d d _ c e l l s _ t o _ p b l o c k [g e t _ p b l o c k s p b _ i n s t _ P a r t i a l A r e a ] 7 [g e t _ c e l l s i n s t _ P a r t i a l A r e a ]; 8 # p r e v e n t p l a c e m e n t of l o g i c t h a t is not a s s i g n e d to the p b l o c k 9 s e t _ p r o p e r t y E X C L U D E _ P L A C E M E N T t r u e 10 [g e t _ p b l o c k s p b _ i n s t _ P a r t i a l A r e a ];

Listing 5.13: In Vivado, we use pblocks to constrain the placement of logic cells.