Módulo de suma de cuadrados

– M ód u lo: U n id ad A ritm ética d e P u nto F ijo - M ód u lo d e su m a d e cu ad rad os – A u tor: In g. Ju an Pab lo H u rtad o Pach eco

–D eclaración d e lib rerías lib rary IE E E ; u se IE E E .S T D _ L O G IC _ 1164.A L L ; u se IE E E .S T D _ L O G IC _ A R IT H .A L L ; u se IE E E .S T D _ L O G IC _ U N S IG N E D .A L L ; – D eclaración d e entid ad entity S u m _ sq u are is Port ( clk : in S T D _ L O G IC ; accu m u late : in S T D _ L O G IC ; en ab le : in S T D _ L O G IC ; in p u t : in S T D _ L O G IC _ V E C T O R (11 d ow nto 0); su m _ sq u are_ d on e : ou t S T D _ L O G IC ; su m _ sq u are_ ou tp u t : ou t S T D _ L O G IC _ V E C T O R (29 d ow nto 0)); en d S u m _ sq u are;

arch itectu re B eh av ioral of S u m _ sq u are is

– D eclaración d e com p on ente d e elevación al cu ad rad o C O M P O N E N T S q u are

P O RT (

d atain : IN std _ logic_ vector(11 d ow nto 0); resu lt : O U T std _ logic_ vector(23 d ow nto 0) );

E N D C O M P O N E N T ;

– D eclaración d e señ ales

sign al su m _ sq u are_ acu m : std _ logic_ vector(29 d ow nto 0):= (oth ers =>’0’);

sign al sq u are_ resu lt: std _ logic_ vector(23 d ow nto 0):= (oth ers =>’0’);

sign al cou nt: std _ logic_ vector(5 d ow nto 0):= (oth ers =>’0’);

sign al state: std _ logic_ vector(1 d ow nto 0):= (oth ers =>’0’);

b egin – P ro ceso d e su m a d e cu ad rad os S u m _ sq u are: p ro cess(clk ) b egin if(en ab le = ’0’) th en state<= "00"; cou nt<= "000000"; su m _ sq u are_ d on e<= ’0’; elsif(risin g_ ed ge(clk )) th en case state is w h en "00-> if(accu m u late = ’1’) th en state<= "01"; en d if; su m _ sq u are_ d on e<= ’0’; w h en "01->

sq u are_ resu lt_ int<= "000000"& sq u are_ resu lt;

state<= "10";

w h en "10->

if(cou nt = "000000") th en

su m _ sq u are_ acu m<= sq u are_ resu lt_ int;

state<= "00";

else

su m _ sq u are_ acu m<= su m _ sq u are_ acu m + sq u are_ resu lt_ int;

if(cou nt = "111111") th en state<= "11"; else state<= "00"; en d if; en d if; cou nt<= cou nt + 1; w h en "11->

su m _ sq u are_ ou tp u t<= su m _ sq u are_ acu m ;

su m _ sq u are_ d on e<= ’1’;

state<= "00";

w h en oth ers => state<= "00"; cou nt<= "000000"; en d case; en d if; en d p ro cess S u m _ sq u are;

– C reación d e in stan cia d e elevación al cu ad rad o S q u are_ 1: S q u are P O RT M A P (

d atain =>in p u t,

resu lt =>sq u are_ resu lt

); en d B eh av ioral;

B.7. Procesador

– D isp ositivo d e d etección d e cán cer cérv ico-u terin o – M ód u lo: P ro cesad or

– A u tor: In g. Ju an Pab lo H u rtad o Pach eco – D eclaración d e lib rerías

lib rary IE E E ; u se IE E E .S T D _ L O G IC _ 1164.A L L ; u se IE E E .S T D _ L O G IC _ A R IT H .A L L ; u se IE E E .S T D _ L O G IC _ U N S IG N E D .A L L ; lib rary U N IS IM ; u se U N IS IM .VC om p on ents.all; –D eclaración d e entid ad entity C AC U _ D ev ice is Port( in p u t_ clk : in std _ logic; A D C _ d 0: in std _ logic; A D C _ d 1: in std _ logic; A D C _ sclk : ou t std _ logic; A D C _ cs: ou t std _ logic; D AC _ sy n c: ou t std _ logic; D AC _ d ou t: ou t std _ logic; D AC _ sclk : ou t std _ logic;

d isp lay 7seg: ou t std _ logic_ vector(3 d ow nto 0); –Vector u tilizad o ú n icam ente p ara los ex p erim entos start_ m easu rem ents: in std _ logic;

op tic_ b lu e: ou t std _ logic; op tic_ green : ou t std _ logic; tissu e_ h ealthy : ou t std _ logic; tissu e_ C IN : ou t std _ logic; tissu e_ can cer: ou t std _ logic; L E D _ listo: ou t std _ logic;

tx : ou t std _ logic –S eñ al u tilizad o ú n icam ente p ara los ex p erim entos );

en d C AC U _ D ev ice;

arch itectu re B eh av ioral of C AC U _ D ev ice is – D eclaración d e com p on entes com p on ent A D C _ M o d u le Port ( clk : in S T D _ L O G IC ; start : in S T D _ L O G IC ; d 0 : in S T D _ L O G IC ; d 1 : in S T D _ L O G IC ; sclk : ou t S T D _ L O G IC ; cs : ou t S T D _ L O G IC ; d on e : ou t S T D _ L O G IC ; d ataou t0 : ou t S T D _ L O G IC _ V E C T O R (11 d ow nto 0); d ataou t1 : ou t S T D _ L O G IC _ V E C T O R (11 d ow nto 0)); en d com p on ent A D C _ M o d u le;

C O M P O N E N T D AC _ M o d u le P O RT ( clk : IN std _ logic; ld ac : IN std _ logic; p d b : IN std _ logic; p d a : IN std _ logic; n a_ b : IN std _ logic;

cr : IN std _ logic_ vector(1 d ow nto 0); d ata : IN std _ logic_ vector(7 d ow nto 0); sclk : O U T std _ logic; sy n c : O U T std _ logic; d ou t : O U T std _ logic ); E N D C O M P O N E N T ; C O M P O N E N T S u m _ sq u are P O RT (

clk : IN std _ logic; accu m u late : IN std _ logic; en ab le : IN std _ logic;

in p u t : IN std _ logic_ vector(11 d ow nto 0); su m _ sq u are_ d on e : O U T std _ logic;

su m _ sq u are_ ou tp u t : O U T std _ logic_ vector(29 d ow nto 0) ); E N D C O M P O N E N T S u m _ sq u are; C O M P O N E N T S q u are_ ro ot P O RT ( x _ in : IN std _ logic_ V E C T O R (30 d ow nto 0); n d : IN std _ logic; x _ ou t: O U T std _ logic_ V E C T O R (14 d ow nto 0); rd y : O U T std _ logic; clk : IN std _ logic); E N D C O M P O N E N T S q u are_ ro ot; C O M P O N E N T sin e_ w ave P O RT ( clo ck : IN std _ logic; en ab le : IN std _ logic;

w ave_ ou t : O U T std _ logic_ vector(7 d ow nto 0) ); E N D C O M P O N E N T ; C O M P O N E N T C lo ck M an ager P O RT ( C L K IN _ IN : IN std _ logic; U S E R _ R S T _ IN : IN std _ logic; C L K D V _ O U T : O U T std _ logic; C L K IN _ IB U FG _ O U T : O U T std _ logic; C L K 0_ O U T : O U T std _ logic; L O C K E D _ O U T : O U T std _ logic ); E N D C O M P O N E N T C lo ck M an ager; C O M P O N E N T C AC U _ R O M _ M em ory P O RT (

electric_ op tic : IN std _ logic;

d ata : O U T std _ logic_ vector(15 d ow nto 0) );

E N D C O M P O N E N T ;

– E ste com p on entes se u sa solo p ara p ru eb as C O M P O N E N T S erial_ Tran sm itter P O RT (

d ato_ entrad a : IN std _ logic_ vector(7 d ow nto 0); w rite_ b u ¤ er : IN std _ logic;

clk : IN std _ logic; serial_ ou t : O U T std _ logic );

E N D C O M P O N E N T ;

–S eñ ales d e relo j

sign al clk 20m h z: std _ logic; sign al clk 50m h z: std _ logic;

–S eñ ales d e A D C

sign al start_ conversion : std _ logic; sign al A D C _ d 1_ int: std _ logic; sign al A D C _ d 0_ int: std _ logic; sign al A D C _ sclk _ int: std _ logic; sign al A D C _ cs_ int: std _ logic;

sign al A D C _ d ataou t0_ int: std _ logic_ vector(11 d ow nto 0); sign al A D C _ d ataou t1_ int: std _ logic_ vector(11 d ow nto 0); sign al A D C _ d on e_ int: std _ logic;

–S eñ ales D AC

sign al D AC _ ld ac_ int: std _ logic; sign al D AC _ p d b _ int: std _ logic; sign al D AC _ p d a_ int: std _ logic; sign al D AC _ n a_ b _ int: std _ logic;

sign al D AC _ cr_ int: std _ logic_ vector(1 d ow nto 0); sign al D AC _ d ata_ int: std _ logic_ vector(7 d ow nto 0); sign al D AC _ sclk _ int: std _ logic;

sign al D AC _ sy n c_ int: std _ logic; sign al D AC _ d ou t_ int: std _ logic;

–S eñ ales A cu m u lad or d e C u ad rad os sign al su m _ sq u are_ d on e_ int: std _ logic;

sign al su m _ sq u are_ ou tp u t_ int: std _ logic_ vector(29 d ow nto 0);

–S eñ ales R aíz C u ad rad a

sign al sq u are_ ro ot_ in p u t: std _ logic_ vector(30 d ow nto 0):= (oth ers =>’0’);

sign al sq u are_ ro ot_ n d : std _ logic:= ’0’;

sign al sq u are_ ro ot_ resu lt: std _ logic_ vector(14 d ow nto 0); sign al sq u are_ ro ot_ rd y : std _ logic;

–S eñ ales M u ltip licad or R aíz C u ad rad a x 3.32

con stant m u lt3_ 32: std _ logic_ vector(17 d ow nto 0):= "001101010100101111"; sign al m u lt_ m easu rem ent: std _ logic_ vector(17 d ow nto 0):= (oth ers =>’0’);

sign al m u lt_ resu lt: std _ logic_ vector(35 d ow nto 0);

–Tran sm isor S erial (S olo p ara p ru eb as)

sign al serial_ in p u t: std _ logic_ vector(7 d ow nto 0):= (oth ers =>’0’);

sign al w rite_ serial: std _ logic:= ’0’;

sign al tran sm it_ d ata: std _ logic_ vector(15 d ow nto 0):= (oth ers =>’0’);

–S eñ ales d e relo j au x iliares sign al electric_ acq u ire: std _ logic; sign al clk 510k h z_ int: std _ logic; sign al on ek h z_ d elay _ int: std _ logic; sign al h z100_ d elay _ int: std _ logic; sign al on em h z_ d elay _ int: std _ logic; sign al start_ d elay : std _ logic:= ’0’; sign al start_ h z100_ d elay : std _ logic:= ’0’; sign al start_ on em h z_ d elay : std _ logic:= ’0’; –C ontad ores

sign al clk 64k h z_ gen _ cou nt: std _ logic_ vector(8 d ow nto 0):= (oth ers =>’0’);

sign al clk 510k h z_ gen _ cou nt: std _ logic_ vector(6 d ow nto 0):= (oth ers =>’0’);

sign al on ek h z_ d elay _ cou nt: std _ logic_ vector(15 d ow nto 0):= (oth ers =>’0’);

sign al h z100_ d elay _ cou nt: std _ logic_ vector(19 d ow nto 0):= (oth ers =>’0’);

sign al on em h z_ d elay _ cou nt: std _ logic_ vector(5 d ow nto 0):= (oth ers =>’0’);

–S eñ ales d e d iagram a d e estad os

sign al state: std _ logic_ vector(5 d ow nto 0):= (oth ers =>’0’);

sign al electric_ m easu rem ent: std _ logic:= ’0’; sign al op tic_ m easu rem ent: std _ logic:= ’0’;

–S eñ ales d e gen erad or sen oid al

sign al sin e_ w ave_ ou tp u t: std _ logic_ vector(7 d ow nto 0); sign al sin e_ w ave_ en ab le: std _ logic:= ’0’;

–R esu ltad os

sign al resu ltad o_ electrico: std _ logic_ vector(15 d ow nto 0):= (oth ers =>’0’);

sign al resu ltad o_ op tico_ ro jo: std _ logic_ vector(15 d ow nto 0):= (oth ers =>’0’);

sign al resu ltad o_ op tico_ verd e: std _ logic_ vector(15 d ow nto 0):= (oth ers =>’0’);

sign al resu ltad o_ op tico_ azu l: std _ logic_ vector(15 d ow nto 0):= (oth ers =>’0’);

–S eñ ales d e m em oria R O M

sign al R O M _ ad d ress: std _ logic_ vector(3 d ow nto 0):= (oth ers =>’0’);

sign al R O M _ d ata: std _ logic_ vector(15 d ow nto 0); sign al R O M _ selector: std _ logic:= ’0’;

b egin D AC _ ld ac_ int<= ’0’; D AC _ p d b _ int<= ’1’; D AC _ p d a_ int<= ’0’; D AC _ n a_ b _ int<= ’0’; D AC _ cr_ int<= "11";

– G en eración d e señ al d e relo j d e 64 K H z clk 64k h z_ gen : p ro cess(clk 20m h z) b egin

if(risin g_ ed ge(clk 20m h z)) th en if(electric_ m easu rem ent = ’1’) th en

if(clk 64k h z_ gen _ cou nt = "100111000") th en electric_ acq u ire<= ’1’;

clk 64k h z_ gen _ cou nt<= (oth ers =>’0’);

else

electric_ acq u ire<= ’0’;

clk 64k h z_ gen _ cou nt<= clk 64k h z_ gen _ cou nt + 1;

en d if; else

electric_ acq u ire<= ’0’;

clk 64k h z_ gen _ cou nt<= (oth ers =>’0’);

en d if; en d if;

– G en eración d e señ al d e relo j d e 510 K H z clk 510k h z_ gen : p ro cess(clk 50m h z) b egin

if(risin g_ ed ge(clk 50m h z)) th en

if(clk 510k h z_ gen _ cou nt = "1100001") th en clk 510k h z_ int<= ’1’;

clk 510k h z_ gen _ cou nt<= (oth ers =>’0’);

else

clk 510k h z_ int<= ’0’;

clk 510k h z_ gen _ cou nt<= clk 510k h z_ gen _ cou nt + 1;

en d if; en d if;

en d p ro cess clk 510k h z_ gen ;

– G en eración d e señ al d e relo j d e 1 K H z on ek h z_ d elay : p ro cess(clk 50m h z) b egin

if(risin g_ ed ge(clk 50m h z)) th en if(start_ d elay = ’1’) th en

if(on ek h z_ d elay _ cou nt = "1100001001100001") th en on ek h z_ d elay _ int<= ’1’;

on ek h z_ d elay _ cou nt<= (oth ers =>’0’);

else

on ek h z_ d elay _ int<= ’0’;

on ek h z_ d elay _ cou nt<= on ek h z_ d elay _ cou nt + 1;

en d if; else

on ek h z_ d elay _ int<= ’0’;

on ek h z_ d elay _ cou nt<= (oth ers =>’0’);

en d if; en d if;

en d p ro cess on ek h z_ d elay ;

– G en eración d e señ al d e relo j d e 100 H z h z100_ d elay : p ro cess(clk 50m h z) b egin

if(risin g_ ed ge(clk 50m h z)) th en if(start_ h z100_ d elay = ’1’) th en

h z100_ d elay _ int<= ’1’;

h z100_ d elay _ cou nt<= (oth ers =>’0’);

else

h z100_ d elay _ int<= ’0’;

h z100_ d elay _ cou nt<= h z100_ d elay _ cou nt + 1;

en d if; else

h z100_ d elay _ int<= ’0’;

h z100_ d elay _ cou nt<= (oth ers =>’0’);

en d if; en d if;

en d p ro cess h z100_ d elay ;

– G en eración d e señ al d e relo j d e 1 M H z on em h z_ d elay : p ro cess(clk 50m h z) b egin

if(risin g_ ed ge(clk 50m h z)) th en if(start_ on em h z_ d elay = ’1’) th en

if(on em h z_ d elay _ cou nt = "110010") th en on em h z_ d elay _ int<= ’1’;

on em h z_ d elay _ cou nt<= (oth ers =>’0’);

else

on em h z_ d elay _ int<= ’0’;

on em h z_ d elay _ cou nt<= on em h z_ d elay _ cou nt + 1;

en d if; else

on em h z_ d elay _ int<= ’0’;

on em h z_ d elay _ cou nt<= (oth ers =>’0’);

en d if; en d if;

en d p ro cess on em h z_ d elay ;

d isp lay 7seg<= "1111"; – S eñ al u sad a solo p ara p ru eb as

start_ conversion<= electric_ acq u ire or op tic_ m easu rem ent;

– C reación d e in stan cias d e com p on entes A D C _ M o d u le_ 1: A D C _ M o d u le p ort m ap ( clk =>clk 20m h z,

start =>start_ conversion ,

d 1 =>A D C _ d 1_ int,

sclk =>A D C _ sclk _ int,

cs =>A D C _ cs_ int,

d on e =>A D C _ d on e_ int,

d ataou t0 =>A D C _ d ataou t0_ int,

d ataou t1 =>A D C _ d ataou t1_ int

); D AC _ ld ac_ int<= ’0’; D AC _ p d b _ int<= ’1’; D AC _ p d a_ int<= ’0’; D AC _ n a_ b _ int<= ’0’; D AC _ cr_ int<= "11"; D AC _ M o d u le_ 1: D AC _ M o d u le P O RT M A P ( clk =>clk 50m h z, ld ac =>D AC _ ld ac_ int, p d b =>D AC _ p d b _ int, p d a =>D AC _ p d a_ int, n a_ b =>D AC _ n a_ b _ int, cr =>D AC _ cr_ int,

d ata =>D AC _ d ata_ int,

sclk =>D AC _ sclk _ int, sy n c =>D AC _ sy n c_ int, d ou t =>D AC _ d ou t_ int ); S u m _ sq u are_ 1: S u m _ sq u are P O RT M A P ( clk =>clk 20m h z,

accu m u late =>A D C _ d on e_ int,

en ab le =>electric_ m easu rem ent,

in p u t =>A D C _ d ataou t0_ int,

su m _ sq u are_ d on e =>su m _ sq u are_ d on e_ int,

su m _ sq u are_ ou tp u t =>su m _ sq u are_ ou tp u t_ int

);

S q u are_ ro ot_ 1: S q u are_ ro ot P O RT M A P ( x _ in =>sq u are_ ro ot_ in p u t,

n d =>sq u are_ ro ot_ n d ,

rd y =>sq u are_ ro ot_ rd y, clk =>clk 50m h z ); M u lt_ S q u arero otX 332: M U LT 18X 18 p ort m ap ( P =>m u lt_ resu lt, A =>m u lt3_ 32,

B =>m u lt_ m easu rem ent

);

D AC _ d ata_ int<= sin e_ w ave_ ou tp u t;

sin e_ w ave_ 1: sin e_ w ave P O RT M A P ( clo ck =>clk 510k h z_ int,

en ab le =>sin e_ w ave_ en ab le,

w ave_ ou t =>sin e_ w ave_ ou tp u t

);

C AC U _ RO M _ M em ory _ 1: C AC U _ R O M _ M em ory P O RT M A P ( ad d ress =>R O M _ ad d ress,

d ata =>R O M _ d ata,

electric_ op tic =>R O M _ selector

);

– In stan cia u sad a solo p ara p ru eb as

S erial_ Tran sm itter_ 1: S erial_ Tran sm itter P O RT M A P ( d ato_ entrad a =>serial_ in p u t,

w rite_ b u ¤ er =>w rite_ serial,

serial_ ou t =>tx , clk =>clk 50m h z ); C lo ck M an ager_ 1: C lo ck M an ager P O RT M A P ( C L K IN _ IN =>in p u t_ clk , U S E R _ R S T _ IN =>’0’, C L K D V _ O U T =>clk 20m h z, C L K IN _ IB U FG _ O U T =>op en , C L K 0_ O U T =>clk 50m h z, L O C K E D _ O U T =>op en );

– A lgoritm o d e m ed ición y d iagn óstico M easu rem ent_ d iagn osis: p ro cess(clk 50m h z) b egin if(risin g_ ed ge(clk 50m h z)) th en case state is w h en "000000-> L E D _ listo<= ’1’; op tic_ red<= ’0’; op tic_ green<= ’0’; op tic_ b lu e<= ’0’;

if(start_ m easu rem ents = ’1’) th en start_ d elay<= ’1’;

state<= "000001";

R O M _ selector<= ’0’;

R O M _ ad d ress<= (oth ers =>’0’);

en d if; w h en "000001->

L E D _ listo<= ’0’;

if(on ek h z_ d elay _ int = ’1’) th en start_ d elay<= ’0’;

electric_ m easu rem ent<= ’1’;

sin e_ w ave_ en ab le<= ’1’;

state<= "000010";

en d if; w h en "000010->

if(su m _ sq u are_ d on e_ int = ’1’) th en electric_ m easu rem ent<= ’0’;

sin e_ w ave_ en ab le<= ’0’;

sq u are_ ro ot_ in p u t<= ’0’ & su m _ sq u are_ ou tp u t_ int;

sq u are_ ro ot_ n d<= ’1’;

state<= "000011";

en d if; w h en "000011->

sq u are_ ro ot_ n d<= ’0’;

if(sq u are_ ro ot_ rd y = ’1’) th en

m u lt_ m easu rem ent<= "0000"& sq u are_ ro ot_ resu lt(13 d ow nto 0);

state<= "000100";

en d if; w h en "000100->

resu ltad o_ electrico<= m u lt_ resu lt(29 d ow nto 14);

op tic_ red<= ’1’;

start_ h z100_ d elay<= ’1’;

state<= "000101";

w h en "000101->

if(h z100_ d elay _ int = ’1’) th en start_ h z100_ d elay<= ’0’;

op tic_ m easu rem ent<= ’1’;

state<= "000110";

en d if; w h en "000110->

if(A D C _ d on e_ int = ’1’) th en op tic_ m easu rem ent<= ’0’;

m u lt_ m easu rem ent<= "0000"& A D C _ d ataou t1_ int & "00";

state<= "000111";

en d if; w h en "000111->

op tic_ red<= ’0’;

start_ on em h z_ d elay<= ’1’;

resu ltad o_ op tico_ ro jo<= m u lt_ resu lt(29 d ow nto 14);

state<= "001000";

w h en "001000->

if(on em h z_ d elay _ int = ’1’) th en start_ on em h z_ d elay<= ’0’; op tic_ b lu e<= ’1’; start_ h z100_ d elay<= ’1’; state<= "001001"; en d if; w h en "001001->

if(h z100_ d elay _ int = ’1’) th en start_ h z100_ d elay<= ’0’;

op tic_ m easu rem ent<= ’1’;

state<= "001010";

en d if; w h en "001010->

if(A D C _ d on e_ int = ’1’) th en op tic_ m easu rem ent<= ’0’;

m u lt_ m easu rem ent<= "0000"& A D C _ d ataou t1_ int & "00";

state<= "001011";

w h en "001011->

op tic_ b lu e<= ’0’;

start_ on em h z_ d elay<= ’1’;

resu ltad o_ op tico_ azu l<= m u lt_ resu lt(29 d ow nto 14);

state<= "001100";

w h en "001100->

if(on em h z_ d elay _ int = ’1’) th en start_ on em h z_ d elay<= ’0’; op tic_ green<= ’1’; start_ h z100_ d elay<= ’1’; state<= "001101"; en d if; w h en "001101->

if(h z100_ d elay _ int = ’1’) th en start_ h z100_ d elay<= ’0’;

op tic_ m easu rem ent<= ’1’;

state<= "001110";

en d if; w h en "001110->

if(A D C _ d on e_ int = ’1’) th en op tic_ m easu rem ent<= ’0’;

m u lt_ m easu rem ent<= "0000"& A D C _ d ataou t1_ int & "00";

state<= "001111";

en d if; w h en "001111->

op tic_ green<= ’0’;

start_ on em h z_ d elay<= ’1’;

resu ltad o_ op tico_ verd e<= m u lt_ resu lt(29 d ow nto 14);

state<= "010000";

w h en "010000->

if(on em h z_ d elay _ int = ’1’) th en start_ on em h z_ d elay<= ’0’;

state<= "010001";

R O M _ selector<= ’1’;

R O M _ ad d ress<= (oth ers =>’0’);

en d if; w h en "010001->

if(resu ltad o_ op tico_ ro jo<R O M _ d ata) th en

tissu e_ h ealthy<= ’0’;

tissu e_ can cer<= ’1’;

state<= "010100";

else

R O M _ selector<= ’0’;

R O M _ ad d ress<= (oth ers =>’0’);

state<= "010010";

en d if; w h en "010010->

if(resu ltad o_ electrico<= R O M _ d ata) th en

tissu e_ h ealthy<= ’0’;

tissu e_ C IN<= ’0’;

tissu e_ can cer<= ’1’;

state<= "010100"; else R O M _ selector<= ’0’; R O M _ ad d ress<= R O M _ ad d ress + 1; state<= "010011"; en d if; w h en "010011->

if(resu ltad o_ electrico<= R O M _ d ata) th en

tissu e_ h ealthy<= ’0’;

tissu e_ C IN<= ’1’;

tissu e_ can cer<= ’0’;

state<= "010100";

else

tissu e_ h ealthy<= ’1’;

tissu e_ C IN<= ’0’;

tissu e_ can cer<= ’0’;

state<= "010100";

en d if;

w h en "010100->– D esd e aq u í los estad os se u san p ara tran sm isión serial, y n o form an p arte d el algoritm o

w rite_ serial<= ’1’;

serial_ in p u t<= "000000"& resu ltad o_ electrico(15 d ow nto 14);

state<= "010101";

w h en "010101->

serial_ in p u t<= resu ltad o_ electrico(13 d ow nto 6);

state<= "010110";

w h en "010110->

serial_ in p u t<= resu ltad o_ electrico(5 d ow nto 0) & "00";

w h en "010111->

serial_ in p u t<= "000000"& resu ltad o_ op tico_ ro jo(15 d ow nto 14);

state<= "011000";

w h en "011000->

serial_ in p u t<= resu ltad o_ op tico_ ro jo(13 d ow nto 6);

state<= "011001";

w h en "011001->

serial_ in p u t<= resu ltad o_ op tico_ ro jo(5 d ow nto 0) & "00";

state<= "011010";

w h en "011010->

serial_ in p u t<= "000000"& resu ltad o_ op tico_ azu l(15 d ow nto 14);

state<= "011011";

w h en "011011->

serial_ in p u t<= resu ltad o_ op tico_ azu l(13 d ow nto 6);

state<= "011100";

w h en "011100->

serial_ in p u t<= resu ltad o_ op tico_ azu l(5 d ow nto 0) & "00";

state<= "011101";

w h en "011101->

serial_ in p u t<= "000000"& resu ltad o_ op tico_ verd e(15 d ow nto 14);

state<= "011110";

w h en "011110->

serial_ in p u t<= resu ltad o_ op tico_ verd e(13 d ow nto 6);

state<= "011111";

w h en "011111->– A q u í terim in an los estad os u tilizad os p ara la tran sm isión serial

serial_ in p u t<= resu ltad o_ op tico_ verd e(5 d ow nto 0) & "00";

state<= "100000";

w h en "100000->

w rite_ serial<= ’0’;

if(start_ m easu rem ents = ’0’) th en state<= "000000"; en d if; w h en oth ers => state<= "000000"; en d case; en d if;

en d p ro cess M easu rem ent_ d iagn osis;

IB U F _ A D C _ d 0 : IB U F gen eric m ap (

IO S TA N D A R D =>"LVC M O S 33")

p ort m ap (

O =>A D C _ d 0_ int, – B u ¤ er ou tp u t

I =>A D C _ d 0 – B u ¤ er in p u t (con n ect d irectly to top -level p ort)

); IB U F _ A D C _ d 1 : IB U F gen eric m ap ( IO S TA N D A R D =>"LVC M O S 33") p ort m ap ( O =>A D C _ d 1_ int, – B u ¤ er ou tp u t

I =>A D C _ d 1 – B u ¤ er in p u t (con n ect d irectly to top -level p ort)

); O B U F _ A D C _ sclk : O B U F gen eric m ap ( D R IV E =>2, IO S TA N D A R D =>"LVC M O S 33", S L E W =>"FA S T ") p ort m ap (

O =>A D C _ sclk , – B u ¤ er ou tp u t (con n ect d irectly to top -level p ort)

I =>A D C _ sclk _ int – B u ¤ er in p u t ); O B U F _ A D C _ cs : O B U F gen eric m ap ( D R IV E =>2, IO S TA N D A R D =>"LVC M O S 33", S L E W =>"FA S T ") p ort m ap (

O =>A D C _ cs, – B u ¤ er ou tp u t (con n ect d irectly to top -level p ort)

I =>A D C _ cs_ int – B u ¤ er in p u t ); O B U F _ D AC _ sy n c : O B U F gen eric m ap ( D R IV E =>2, IO S TA N D A R D =>"LVC M O S 33",

S L E W =>"FA S T ")

p ort m ap (

O =>D AC _ sy n c, – B u ¤ er ou tp u t (con n ect d irectly to top -level p ort)

I =>D AC _ sy n c_ int – B u ¤ er in p u t ); O B U F _ D AC _ d ou t : O B U F gen eric m ap ( D R IV E =>2, IO S TA N D A R D =>"LVC M O S 33", S L E W =>"FA S T ") p ort m ap (

O =>D AC _ d ou t, – B u ¤ er ou tp u t (con n ect d irectly to top -level p ort)

I =>D AC _ d ou t_ int – B u ¤ er in p u t ); O B U F _ D AC _ sclk : O B U F gen eric m ap ( D R IV E =>2, IO S TA N D A R D =>"LVC M O S 33", S L E W =>"FA S T ") p ort m ap (

O =>D AC _ sclk , – B u ¤ er ou tp u t (con n ect d irectly to top -level p ort)

I =>D AC _ sclk _ int – B u ¤ er in p u t

);

Apéndice C

Hojas de datos

A continuación se presentan las hojas de datos de los circuitos integrados utilizados en el diseño del dispositivo de esta tesis. Para cada circuito integrado se muestran sus características eléctricas tales como rangos de voltajes y consumo de corriente, así como la asignación de pines y diagramas de tiempo según sea necesario.

Micropower, Single- and Dual-Supply,

Rail-to-Rail Instrumentation Amplifier

AD627

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

FEATURES

Micropower, 85 µA maximum supply current Wide power supply range (+2.2 V to ±18 V) Easy to use

Gain set with one external resistor Gain range 5 (no resistor) to 1000 Higher performance than discrete designs Rail-to-rail output swing

High accuracy dc performance

0.03% typical gain accuracy (G = +5) (AD627A) 10 ppm/°C typical gain drift (G = +5)

125 µV maximum input offset voltage (AD627B dual supply) 200 µV maximum input offset voltage (AD627A dual supply) 1 µV/°C maximum input offset voltage drift (AD627B) 3 µV/°C maximum input offset voltage drift (AD627A) 10 nA maximum input bias current

Noise: 38 nV/√Hz RTI noise @ 1 kHz (G = +100) Excellent ac specifications

AD627A: 77 dB minimum CMRR (G = +5) AD627B: 83 dB minimum CMRR (G = +5) 80 kHz bandwidth (G = +5)

135 µs settling time to 0.01% (G = +5, 5 V step)

APPLICATIONS

4 to 20 mA loop-powered applications

In document Diseño Electrónico de Dispositivo de Autodiagnóstico de Cáncer Cérvico-Uterino-Edicioón Única (página 101-126)