The GICC_IAR characteristics are:
Purpose The processor reads this register to obtain the interrupt ID of the signaled interrupt. This read acts as an acknowledge for the interrupt.
Usage constraints When GICC_CTLR.AckCtl is set to 0 in a GICv2 implementation that does not include the Security Extensions, if the highest priority pending interrupt is in Group 1, the interrupt ID 1022 is returned.
Configurations This register is available in all configurations of the GIC. If the GIC implements the Security Extensions:
• this register is Common.
• the GICC_AIAR is an alias of the Non-secure view of this register. Attributes See the register summary in Table 4-2 on page 4-76.
Figure 4-27 shows the IAR bit assignments.
Figure 4-27 GICC_IAR bit assignments
Table 4-34 shows the IAR bit assignments.
A read of the GICC_IAR returns the interrupt ID of the highest priority pending interrupt for the CPU interface. The read returns a spurious interrupt ID of 1023 if any of the following apply:
• forwarding of interrupts by the Distributor to the CPU interface is disabled • signaling of interrupts by the CPU interface to the connected processor is disabled
• no pending interrupt on the CPU interface has sufficient priority for the interface to signal it to the processor.
Note
The following sequence of events is an example of when the GIC returns an interrupt ID of 1023, and shows how reads of the GICC_IAR can be timing critical:
1. A peripheral asserts a level-sensitive interrupt.
2. The interrupt has sufficient priority and therefore the GIC signals it to a targeted processor.
3. The peripheral deasserts the interrupt. Because there is no other pending interrupt of sufficient priority, the
31 9 0 Reserved 10 Interrupt ID 12 13 CPUID
Table 4-34 GICC_IAR bit assignments
Bit Name Function
[31:13] - Reserved.
[12:10] CPUID For SGIs in a multiprocessor implementation, this field identifies the processor that requested the interrupt. It returns the number of the CPU interface that made the request, for example a value of 3 means the request was generated by a write to the
GICD_SGIR on CPU interface 3. For all other interrupts this field is RAZ. [9:0] Interrupt ID The interrupt ID.
4 Programmers’ Model
4.4 CPU interface register descriptions
4. Before it has recognized the deassertion of the interrupt request from stage 3, the targeted processor reads the GICC_IAR. Because there is no interrupt with sufficient priority to signal to the processor, the GIC returns the spurious ID value of 1023.
The determination of the returned interrupt ID is more complex if the GIC supports interrupt grouping, see Effect of interrupt grouping on reads of the GICC_IAR.
A non-spurious interrupt ID returned by a read of the GICC_IAR is called a valid interrupt ID.
When the GIC returns a valid interrupt ID to a read of the GICC_IAR it treats the read as an acknowledge of that interrupt and, as a side-effect of the read, changes the interrupt status from pending to active, or to active and pending if the pending state of the interrupt persists. Normally, the pending state of an interrupt persists only if the interrupt is level-sensitive and remains asserted.
For every read of a valid Interrupt ID from the GICC_IAR, the connected processor must perform a matching write to the GICC_EOIR.
Note
• For compatibility with possible extensions to the GIC architecture specification, ARM recommends that software preserves the entire register value read from the GICC_IAR, and writes that value back to the
GICC_EOIR when it has completed its processing of the interrupt.
• Although multiple target processors might attempt to read the GICC_IAR at any time, in GICv2 only one processor can obtain a valid interrupt ID, see Implications of the 1-N model on page 3-41 for more information.
Effect of interrupt grouping on reads of the GICC_IAR Note
This section does not apply to GICV_IAR, the corresponding register in the virtual CPU interface.
When a GIC implementation supports interrupt grouping, whether a read of the GICC_IAR returns a valid interrupt ID depends on:
• whether there is a pending interrupt of sufficient priority for it to be signaled to the processor, and if so, whether:
— the highest priority pending interrupt is a Group 0 or a Group 1 interrupt — interrupt signaling is enabled for that interrupt group.
• if the GIC implements the Security Extensions, whether the GICC_IAR read access is Secure or Non-secure • the value of the GICC_CTLR.AckCtl bit.
Reads of the GICC_IAR that do not return a valid interrupt ID returns a spurious interrupt ID, ID 1022 or 1023, see
Special interrupt numbers when a GIC supports interrupt grouping on page 3-50. Table 4-35 shows all possible GICC_IAR reads for a GIC that supports interrupt grouping on a CPU interface that implements the Security Extensions. For a GICv2 CPU interface that does not implement the Security Extensions, all entries except those for Non-secure GICC_IAR reads apply.
Table 4-35 Effect of interrupt grouping and the Security Extensions on reads of GICC_IAR
State GICC_IAR read GICC_CTLR.AckCtl Returned interrupt ID
Highest priority pending interrupta is Group 1 Non-secure x ID of Group 1 interrupt
Secure 1 ID of Group 1 interrupt
4 Programmers’ Model 4.4 CPU interface register descriptions
The following pseudocode shows the effects of the GIC Security Extensions on accesses to this register: // ReadGICC_IAR()
// ============== //
// Value of GICC_IAR read by a CPU access //
bits(32) ReadGICC_IAR(integer cpu_id)
pendID = HighestPriorityPendingInterrupt(cpu_id);
if ( IsGrp0Int(pendID) && (GICD_CTLR.EnableGrp0 == '0' || GICC_CTLR.EnableGrp0 == '0')) || (!IsGrp0Int(pendID) && (GICD_CTLR.EnableGrp1 == '0' || GICC_CTLR.EnableGrp1 == '0')) then
pendID = 1023; // If the highest priority isn't enabled, then no interrupt if pendID != 1023 then // An enabled interrupt is pending
if IsGrp0Int(pendID) then // Highest priority is Group 0 if NS_access then
pendID = 1023;
else // Highest priority is Group 1 if !NS_access && (GICC_CTLR[cpu_id].AckCtl == '0') then pendID = 1022;
cpuID = 0; // Must be zero for non-SGI interrupts if pendID < 16 then // 0 .. 15 are Software Generated Interrupts sgiID = SGI_CpuID(pendID); // value is IMPLEMENTATION DEFINED
if pendID < 1020 then // Check that it is not a spurious interrupt AcknowledgeInterrupt(pendID); // Set active and attempt to clear pending
rval = 0;
rval<12:10> = sgiID; rval<9:0> = pendID; return(rval);
Highest priority pending interrupta is Group 0 Non-secure x Interrupt ID 1023
Secure x ID of Group 0 interrupt
No pending interruptsa x x Interrupt ID 1023
Interrupt signaling of the required interrupt group by CPU interface disabled
x x Interrupt ID 1023
a. Of sufficient priority to be signaled to the processor if signaling by the CPU interface is enabled.
Table 4-35 Effect of interrupt grouping and the Security Extensions on reads of GICC_IAR (continued)
4 Programmers’ Model
4.4 CPU interface register descriptions