In Fig. 48 it is possible that m2 – which is traveling on C2 – arrives at F BEastj+1 before Rj signals RBin,Eastj+1 to remove C1’s reservation. In this case, C1 may get realized at Rj+1, thereby misrouting m2 on C1.
To prevent misrouting, Rj+1’s east input port should check that m2 is traveling on the correct circuit. In general, at any router, Ri, each input port, π, checks that both the destination and the id of the outstanding request that reserved the currently realized circuit match those of the next message in F Bi
π. To retain one cycle per hop latency on the data plane, the comparisons of the destination and the id of the outstanding request are performed in parallel to the message’s head flit traversing the switch to the next router.
Corrective Action: In Fig. 48if the comparisons indicate that m2 is being misrouted, Rj+1 stops sending m2 and does not remove m2’s head flit from F BEastj+1. As for the input port on the next router on C1’s path, it will be signaled to discard m2’s head flit as follows: each router’s input port receives a data valid signal, which indicates whether a flit is being received during the current cycle. The results of comparing the destination and the id of the outstanding request are logically ANDED with the data valid signal of the next input port on the realized circuit’s path. Because the comparison failed, the data valid signal would be cleared causing the next input port to discard m2’s head flit.
Further, Section 6.2.1indicates that RBj+1in,Eastwill receive a signal from Rj to remove C1. However, if misrouting is detected before receiving the signal, the one-flit remove conflicting circuit message can be sent at the next cycle instead of waiting for the signal from Rj. With this optimization, RBj+1in,East would have to ignore the next remove circuit signal that Rj sends.
After sending the remove conflicting circuit message, normal operation of Rj+1 resumes, which includes: RBin,Eastj+1 finding the next reservation with the earliest EUC (C2 in the example), realizing that circuit, and sending the buffered message on the circuit (sending m2 on C2).
(a)
(b)
Figure 49: A circular dependency that causes deadlock. The events are numbered to help explain how the deadlock develops.
6.3 AVOIDING DEADLOCK
In the proposed scheme, each of the control and data planes can be designed to avoid deadlock. A 2D mesh topology is assumed where the control plane uses X-Y routing and the data plane uses Y-X routing. The routers of the data plane have two different kinds of buffers: flit buffers for storing messages (or packets), and reservation buffers for storing circuit reservations. These two types of buffers have a dependence relationship. On the data plane, messages travel on circuits, which require space in the circuit reservation buffers. Similarly, new reservations require free space in the RBs. RB space becomes available only when messages are able to advance so that circuit reservations are utilized and removed from the RBs. Because circuits are reserved backwards; from destination to source, a circular dependency may develop causing potential deadlock in the NoC, as in the following scenario: In Fig.49, a data request is attempting to reserve a new circuit, C1. Unfortunately, when the request arrives at router Ra, there is no free space in the RB of C1’s required input port, RBa
in,N orth. If the request waits, free space may become available allowing C1 to be reserved and allowing the request to advance to its destination. Free space becomes available only if the next message, m, in F Ba
N orth is able to exit Ra, thus making room for C1’s reservation. However, m may be blocked and unable to advance due to a full buffer at the input port of the next router on m’s path. Let m2 be the message at the head of the chain of blocked messages and assume that m2 is stopped at router Rz and is traveling on circuit C2. A circular dependency occurs if m2 is unable to move because C2 cannot be realized at Rz before the new circuit being reserved, C1, is consumed at the same router, Rz. An example of this might be if C1 and C2 share the west output port at Rz, and C1 has an earlier EUC than C2. It can be detected that a deadlock may have developed if a request is unable to reserve a circuit due to unavailability of RB space and this situation persists for a specified number of cycles (i.e., a timeout mechanism).
Resolving this potential deadlock is similar to handling a reservation conflict (Sec- tion6.2.2): the router at which the request is unable to make the reservation (Ra in Fig.49) signals the last input port’s RB at which C1 was successfully reserved to mark C1 for re- moval, and the request is allowed to proceed to its destination without reserving C1, thus
breaking the deadlock. Note that C1’s reservation in the signaled RB is not necessarily the one with the earliest EUC. Consequently, C1’s reservation may not be released immediately; rather it is marked for removal so that when it becomes the earliest one in the RB, a remove conflicting reservation message is injected to consume the partially reserved C1.